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 M32C/82 Group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
REJ03B0032-0120Z Rev.1.20 Jun. 01, 2004
1. Overview
The M32C/82 group microcomputer is a single-chip control unit that utilizes high-performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/82 group is available in 144-pin and 100pin plastic molded LQFP/QFP packages. With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed. It incorporates a multiplier and DMAC adequate for office automation, communication devices and industrial equipments and other high-speed processing applications.
1.1 Applications
Audio, cameras, office equipment, communications equipment, portable equipment, etc.
Rev.1.00 Jun. 01, 2004 page 1
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M32C/82 Group
1. Overview
1.2 Difference between the M32C/82 Group and the M32C/83 Group
The M32/C82 group microcomputer has less peripheral functions than the M32C/83 group miccrocomputer. The intelligent I/O group 3, CAN and the A/D1 converter are not provided in the M32C/82 group. Interrupt requests, and as a result interrupts, DMAC, and DMACII, caused by these peripheral functions are not available in the M32C/82 group.
Rev.1.20 Jun. 01, 2004 page 2
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M32C/82 Group
1. Overview
1.2 Performance Outline
Tables 1.1 and 1.2 list performance outlines of the M32C/82 group. Table 1.1 M32C/82 Group Performance (144-Pin Package)
CPU Item Basic instructions Shortest instruction execution time Performance 108 instructions 33 ns (f(BCLK)=30 MHz, VCC=4.2 V to 5.5 V) 50 ns (f(BCLK)=20 MHz, VCC=3.0 V to 5.5 V) Single-chip mode, Memory expansion mode and Microprocessor mode 16 Mbytes See Table 1.3 123 I/O pins and 1 input pin Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Time measurement function: 16 bits x 12 channels Waveform generating function: 16 bits x 20 channels Communication function (Clock synchronous serial I/O, Clock asynchronous serial I/O, HDLC data processing, Clock synchronous variable length serial I/O, IEBus(1)) 5 channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2) 10-bit A/D converter: 1 circuit, 34 channels 8 bits x 2 channels 4 channels Can be activated by all peripheral function interrupt factors Immediate transfer, Calculation transfer and Chain transfer functions _______ _______ CAS-before-RAS refresh, self-refresh, EDO, FP CRC-CCITT 16 bits x 16 bits 15 bits x 1 channel (with prescaler) 41 internal and 8 external sources, 5 software sources Interrupt priority level: 7 4 circuits Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator must be connected externally Main clock oscillation stop detect function 4.2 V to 5.5 V (f(BCLK)=30 MHz) 3.0 V to 5.5 V (f(BCLK)=20 MHz, through VDC) 3.0 V to 3.6 V (f(BCLK)=20 MHz, not through VDC) 28 mA (VCC=5 V, f(BCLK)=30 MHz) 17 mA (VCC=3.3 V, f(BCLK)=20 MHz) 470 A (VCC=5 V, f(XCIN)=32 kHz, in wait mode) 340 A (VCC=3.3 V, f(XCIN)=32 kHz, through VDC in wait mode) 5.0 A (VCC=3.3 V, f(XCIN)=32 kHz, not through VDC in wait mode) 0.4 A (VCC=5 V, f(XCIN)=32 kHz, in stop mode) 0.4 A (VCC=3.3 V, f(XCIN)=32 kHz, in stop mode) -20 to 85oC, -40 to 85oC (optional) 144-pin plastic molded LQFP
Operation mode Address space Memory capacity Peripheral Port function Multifunction timer Intelligent I/O
Serial I/O
A/D converter D/A converter DMAC DMAC II DRAMC CRC calculation circuit XY converter Watchdog timer Interrupt Clock generating circuit
Oscillation stop detect function Electric Supply voltage characteristics Power consumption
Operating ambient temperature Package
NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. All options are on a request basis.
Rev.1.20 Jun. 01, 2004 page 3
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M32C/82 Group
1. Overview
Table 1.2 M32C/82 Group Performance (100-Pin Package)
CPU Item Basic instructions Shortest instruction execution time Performance 108 instructions 33 ns (f(BCLK)=30 MHz, VCC=4.2 V to 5.5 V) 50 ns (f(BCLK)=20 MHz, VCC=3.0 V to 5.5 V) Single-chip mode, Memory expansion mode and Microprocessor mode 16 Mbytes See Table 1.3 87 I/O pins and 1 input pin Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Time measurement function: 16 bits x 5 channels Waveform generating function: 16 bits x 8 channels Communication function (Clock synchronous serial I/O, Clock asynchronous serial I/O, HDLC data processing, Clock synchronous variable length serial I/O, IEBus(1)) 5 channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2) 10-bit A/D converter: 1 circuit, 26 channels 8 bits x 2 channels 4 channels Can be activated by all peripheral function interrupt factors Immediate transfer, Calculation transfer and Chain transfer functions
_______ _______
Operation mode Address space Memory capacity Peripheral Port function Multifunction timer Intelligent I/O
Serial I/O
A/D converter D/A converter DMAC DMAC II DRAMC CRC calculation circuit X Y converter Watchdog timer Interrupt Clock generating circuit
Oscillation stop detect function Electric Supply voltage characteristics Power consumption
Operating ambient temperature Package NOTES:
CAS-before-RAS refresh, self-refresh, EDO, FP CRC-CCITT 16 bits x 16 bits 15 bits x 1 channel (with prescaler) 41 internal and 8 external sources, 5 software sources Interrupt priority level: 7 4 circuits Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator must be connected externally Main clock oscillation stop detect function 4.2 V to 5.5 V (f(BCLK)=30 MHz) 3.0 V to 5.5 V (f(BCLK)=20 MHz, through VDC) 3.0 V to 3.6 V (f(BCLK)=20 MHz, not through VDC) 28 mA (VCC=5 V, f(BCLK)=30 MHz) 17 mA (VCC=3.3 V, f(BCLK)=20 MHz) 470 A (VCC=5 V, f(XCIN)=32 kHz, in wait mode) 340 A (VCC=3.3 V, f(XCIN)=32 kHz, through VDC in wait mode) 5.0 A (VCC=3.3 V, f(XCIN)=32 kHz, not through VDC in wait mode) 0.4 A (VCC=5 V, f(XCIN)=32 kHz, in stop mode) 0.4 A (VCC=3.3 V, f(XCIN)=32 kHz, in stop mode) -20 to 85oC, -40 to 85oC (optional) 100-pin plastic molded LQFP/QFP
1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. All options are on a request basis.
Rev.1.20 Jun. 01, 2004 page 4
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M32C/82 Group
1. Overview
1.3 Block Diagram
Figure 1.1 shows a block diagram of the M32C/82 group microcomputer. The M32C/82 group microcomputer contains ROM and RAM as memory to store instructions and data, CPU to execute calculations and peripheral functions such as interrupt, timer, serial I/O, DMAC, CRC calculation circuit, A/D converter, D/A converter, DRAMC, intelligent I/O and ports.
8
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Peripheral functions
Timer (16 bits) Timer A 5 channels Timer B 6 channels Three-phase motor control circuit Watchdog timer (15 bits) D/A converter (8-bit x 2 circuits)
A/D converter 1 circuit Standard 10 inputs Maximum 34 inputs(2) UART/Clock synchronous serial I/O 5 channels XY converter 16 bits x 16 bits CRC calculation circuit (CCITT) X16+X12+X5+1
Clock generating circuit XIN - XOUT XCIN - XCOUT On-chip oscillator PLL frequency synthesizer DMAC DMACII
DRAMC
Intelligent I/O ( 3 groups ) Time measurement 12 channels Wave generating 20 channels(2) Communication function Clock synchronous serial I/O, UART, IEBus, HDLC data processing
(2)
M32C/80 series CPU core
R0H R1H R2 R3 A0 A1 FB SB R0L R1L FLG INTB ISP USP PC SVF SVP VCT
Memory ROM
RAM
Multiplier
Port P15
Port P14
Port P13
Port P12
Port P11
Port P10
Port P9
P85
Port P8
8
7
8
8
5
8
8
7
(Note1) NOTES: 1. Ports P11 to P15 are provided in the 144-pin package only. 2. Included in the 144-pin package only.
Figure 1.1 M32C/82 Group Block Diagram
Rev.1.20 Jun. 01, 2004 page 5
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M32C/82 Group
1. Overview
1.4 Product Information
Renesas plans to release the following products in the M32C/82 group: (1) Support for the masked ROM version (2) ROM/RAM capacity (3) Package 100P6S-A : Plastic molded QFP 100P6Q-A : Plastic molded LQFP 144P6Q-A : Plastic molded LQFP
RAM size (Byte) M30828MH-XXXGP 31K M30826MH-XXXGP M30826MH-XXXFP M30825MW-XXXGP 24K M30823MW-XXXGP M30823MW-XXXFP 320K M30825MH-XXXGP M30823MH-XXXGP M30823MH-XXXFP 384K ROM size (Byte)
Figure 1.2 ROM/RAM
Table 1.3 M32C/82 Group
Type number M30825MW-XXXGP M30823MW-XXXGP M30823MW-XXXFP M30825MH-XXXGP M30823MH-XXXGP M30823MH-XXXFP M30828MH-XXXGP M30826MH-XXXGP M30826MH-XXXFP 384 Kbytes 31 Kbytes 384 Kbytes 24 Kbytes 320 Kbytes 24 Kbytes ROM capacity RAM capacity Package type 144P6Q-A 100P6Q-A 100P6S-A 144P6Q-A 100P6Q-A 100P6S-A 144P6Q-A 100P6Q-A 100P6S-A Masked ROM Remarks
Rev.1.20 Jun. 01, 2004 page 6
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M32C/82 Group
1. Overview
M30 82 3 M H GP
Package type options: FP = Package 100P6S-A GP = Package 100P6Q-A, 144P6Q-A ROM capacity: W = 320K bytes H = 384K bytes Memory type: M = Masked ROM version Shows RAM capacity, pin count, etc (Value itself has no specific meaning) M32C/82 Group M16C Family
Figure 1.3 Product Numbering System
Rev.1.20 Jun. 01, 2004 page 7
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M32C/82 Group
1. Overview
1.5 Pin Assignments
Figures 1.4 to 1.6 show pin assignments (top view).
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
D8 / P10 AN07 / D7 / P07 AN06 / D6 / P06 AN05 / D5 / P05 AN04 / D4 / P04 P114 OUTC13 / P113 BE1IN / ISRxD1 / OUTC12 / INPC12 / P112 ISCLK1 / OUTC11 / INPC11 / P111 BE1OUT / ISTxD1 / OUTC10 / P110 AN03 / D3 / P03 AN02 / D2 / P02 AN01 / D1 / P01 AN00 / D0 / P00 INPC07 / AN157 / P157 INPC06 / AN156 / P156 OUTC05 / INPC05 / AN155 / P155 OUTC04 / INPC04 / AN154 / P154 INPC03 / AN153 / P153 BE0IN / ISRxD0 / INPC02 / AN152 / P152 ISCLK0 / OUTC01 / INPC01 / AN151 / P151 Vss BE0OUT / ISTxD0 / OUTC00 / INPC00 / AN150 / P150 Vcc KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN3 / P103 AN2 / P102 AN1 / P101 AVss AN0 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97
73
P11 / D9 P12 / D10 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss P30 / A8 ( MA0 ) ( / D8 ) Vcc P120 / OUTC30 / ISTxD3 P121 / OUTC31 / ISCLK3 P122 / OUTC32 / ISRxD3 P123 / OUTC33 P124 / OUTC34 P31 / A9 ( MA1 ) ( / D9 ) P32 / A10 ( MA2 ) ( / D10 ) P33 / A11 ( MA3 ) ( / D11 ) P34 / A12 ( MA4 ) ( / D12 ) P35 / A13 ( MA5 ) ( / D13 ) P36 / A14 ( MA6 ) ( / D14 ) P37 / A15 ( MA7 ) ( / D15 ) P40 / A16 ( MA8 ) P41 / A17 ( MA9 ) Vss P42 / A18 ( MA10 ) Vcc P43 / A19 ( MA11 )
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 11 1 2 3 4 5 6 7 8 9
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56
M32C/82 GROUP
55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
P44 / CS3 / A20 (MA12) P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P125 P126 P127 P50 / WRL / WR / CASL P51 / WRH / BHE / CASH P52 / RD / DW P53 / CLKOUT / BCLK / ALE P130 / OUTC24 P131 / OUTC25 Vcc P132 / OUTC26 Vss P133 / OUTC23 P54 / HLDA / ALE P55 / HOLD P56 / ALE / RAS P57 / RDY P134 / OUTC20 / ISTxD2 / IEOUT P135 / OUTC22 / ISRxD2 / IEIN P136 / OUTC21 / ISCLK2 P137 / OUTC27 P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64(1) P65 / CLK1 Vss P66 / RxD1 / SCL1 / STxD1 Vcc P67 / TxD1 / SDA1 / SRxD1 P70(2, 3)
NOTES: 1. P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2 2. P70 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20 / ISTxD2 / IEOUT 3. P70 and P71 are ports for the N-channel open drain output.
Figure 1.4 Pin Assignment for 144-Pin Package
Rev.1.20 Jun. 01, 2004 page 8
of 80
SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92 IEIN / ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 P146 P145 P144 OUTC17 / INPC17 / P143 OUTC16 / INPC16 / P142 OUTC15 / P141 OUTC14 / P140 BYTE CNVss VCONT / XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc NMI / P85 INT2 / P84 INT1 / P83 INT0 / P82 U / TA4IN / P81 BE0IN / ISRxD0 / INPC02 / U / TA4OUT / P80 ISCLK0 / OUTC01 / INPC01 / TA3IN / P77 BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76 BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72 (3) IEIN / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71
144P6Q-A
M32C/82 Group
1. Overview
Table 1.4 Pin Characteristics for 144-Pin Package
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BYTE 16 CNVSS 17 XCIN/VCONT 18 XCOUT 19 RESET 20 XOUT 21 VSS 22 XIN 23 VCC 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 VCC 40 41 VSS 42 43 44 45 46 47 48 Control pin Port P96 P95 P94 P93 P92 P91 P90 P146 P145 P144 P143 P142 P141 P140 Interrupt pin Timer pin UART pin TxD4/SDA4/SRxD4 CLK4 CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 OUTC20/IEOUT/ISTxD2 IEIN/ISRxD2 Intelligent I/O pin Analog pin ANEX1 ANEX0 DA1 DA0 Bus control pin
TB4IN TB3IN TB2IN TB1IN TB0IN
INPC17/OUTC17 INPC16/OUTC16 OUTC15 OUTC14
P87 P86
P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P137
NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TB5IN/TA0IN TA0OUT CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 OUTC21/ISCLK2 INPC02/ISRxD0/BE0IN INPC01/OUTC01/ISCLK0 INPC00/OUTC00/ISTxD0/BE0OUT INPC12/OUTC12/ISRxD1/BE1IN INPC11/OUTC11/ISCLK1 OUTC10/ISTxD1/BE1OUT OUTC22/ISRxD2/IEIN OUTC20/ISTxD2/IEOUT
OUTC27
Rev.1.20 Jun. 01, 2004 page 9
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M32C/82 Group
1. Overview
Table 1.4 Pin Characteristics for 144-Pin Package (Continued)
Pin No 49 50 51 52 53 54 55 56 57 VSS 58 59 VCC 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 VCC 75 76 VSS 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 VCC 92 93 VSS 94 95 96 Control pin Port P136 P135 P134 P57 P56 P55 P54 P133 P132 P131 P130 P53 P52 P51 P50 P127 P126 P125 P47 P46 P45 P44 P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 P124 P123 P122 P121 P120 P30 P27 P26 P25 AN27 AN26 AN25 A8(MA0)(/D8) A7(/D7) A6(/D6) A5(/D5) OUTC23 OUTC26 OUTC25 OUTC24 CLKOUT/BCLK/ALE RD/DW WRH/BHE/CASH WRL/WR/CASL Interrupt pin Timer pin UART pin Intelligent I/O pin OUTC21/ISCLK2 OUTC22/ISRxD2/IEIN OUTC20/ISTxD2/IEOUT RDY ALE/RAS HOLD HLDA/ALE Analog pin Bus control pin
CS0/A23 CS1/A22 CS2/A21 CS3/A20(MA12) A19(MA11) A18(MA10) A17(MA9) A16(MA8) A15(MA7)(/D15) A14(MA6)(/D14) A13(MA5)(/D13) A12(MA4)(/D12) A11(MA3)(/D11) A10(MA2)(/D10) A9(MA1)(/D9)
Rev.1.20 Jun. 01, 2004 page 10 of 80
M32C/82 Group
1. Overview
Table 1.4 Pin Characteristics for 144-Pin Package (Continued)
Pin No 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 VSS 131 132 VCC 133 134 135 136 137 138 139 140 AVSS 141 142 VREF 143 AVCC 144 Control pin Port P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P114 P113 P112 P111 P110 P03 P02 P01 P00 P157 P156 P155 P154 P153 P152 P151 P150 P107 P106 P105 P104 P103 P102 P101 P100 KI3 KI2 KI1 KI0 INT5 INT4 INT3 Interrupt pin Timer pin UART pin Intelligent I/O pin Analog pin AN24 AN23 AN22 AN21 AN20 Bus control pin A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
AN07 AN06 AN05 AN04 OUTC13 INPC12/OUTC12/ISRxD1/BE1IN INPC11/OUTC11/ISCLK1 OUTC10/ISTxD1/BE1OUT AN03 AN02 AN01 AN00 AN157 AN156 AN155 AN154 AN153 AN152 AN151 AN150 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
D3 D2 D1 D0
INPC07 INPC06 INPC05/OUTC05 INPC04/OUTC04 INPC03 INPC02/ISRxD0/BE0IN INPC01/OUTC01/ISCLK0 INPC00/OUTC00/ISTxD0/BE0OUT
P97
RxD4/SCL4/STxD4
ADTRG
Rev.1.20 Jun. 01, 2004 page 11
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KI0 / AN4 / P104
KI1 / AN5 / P105
KI2 / AN6 / P106
KI3 / AN7 / P107
D0 / AN00 / P00
D1 / AN01 / P01
D2 / AN02 / P02
D3 / AN03 / P03
D4 / AN04 / P04
D5 / AN05 / P05
D6 / AN06 / P06
D7 / AN07 / P07
AN1 / P101
AN2 / P102
AN3 / P103
AN0 / P100
M32C/82 Group
(2)P97
VREF AVss 88 81 98 97 96 95 94 93 92 91 90 89 87 86 85 84 83 82
AVcc 99
100
SRxD4 / SDA4 / TxD4 / ANEX1 / P96 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 76 77 78 79 P11 / D9 P12 / D10 P13 / D11 P14 / D12 80 CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92 IEIN / ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 BYTE CNVss VCONT / XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc NMI / P85 INT2 / P84 INT1 / P83 INT0 / P82 U / TA4IN / P81 BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80 ISCLK0 / OUTC01 / INPC01 / TA3IN / P77 BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76 BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72
P10 / D8
P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss P30 / A8 ( MA0 ) ( / D8 ) Vcc P31 / A9 ( MA1 ) ( / D9 ) P32 / A10 ( MA2 ) ( / D10 ) P33 / A11 ( MA3 ) ( / D11 ) P34 / A12 ( MA4 ) ( / D12 ) P35 / A13 ( MA5 ) ( / D13 ) P36 / A14 ( MA6 ) ( / D14 ) P37 / A15 ( MA7 ) ( / D15 ) P40 / A16 ( MA8 ) P41 / A17 ( MA9 ) P42 / A18 ( MA10 ) P43 / A19 ( MA11 )
Rev.1.20 Jun. 01, 2004 page 12 of 80
NOTES: 1. P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2 2. P97 / ADTRG / RxD4 / STxD4 / SCL4 3. P70 and P71 are ports for the N-channel open drain output.
Figure 1.5 Pin assignment for 100-Pin Package
M32C/82 GROUP
(3)IEIN / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71
(3)IEOUT / ISTxD2 / OUTC20 / SRxD2 / SDA2 / TxD2 / TA0OUT / P70
33
44
31
32
34
35
36
37
38
39
40
41
42
43
45
46
47
48
49
50
100P6S-A
P64(1)
P57 / RDY
P65 / CLK1 P66 / RxD1 / SCL1 / STxD1 P67 / TxD1 / SDA1 / SRxD1
P46 / CS1 / A22
P47 / CS0 / A23
P44 / CS3 / A20 (MA12)
P50 / WRL / WR / CASL
P61 / CLK0
P55 / HOLD
P52 / RD / DW
P45 / CS2 / A21
P56 / ALE / RAS
P54 / HLDA / ALE
P60 / CTS0 / RTS0 / SS0
P51 / WRH / BHE / CASH
P62 / RxD0 / SCL0 / STxD0
P63 / TxD0 / SDA0 / SRxD0
P53 / CLKOUT / BCLK / ALE
1. Overview
M32C/82 Group
1. Overview
P32 / A10 ( MA2 ) ( / D10 )
P34 / A12 ( MA4 ) ( / D12 )
P35 / A13 ( MA5 ) ( / D13 )
P36 / A14 ( MA6 ) ( / D14 )
P20 / A0 ( / D0 ) / AN20
P21 / A1 ( / D1 ) / AN21
P22 / A2 ( / D2 ) / AN22
P23 / A3 ( / D3 ) / AN23
P24 / A4 ( / D4 ) / AN24
P25 / A5 ( / D5 ) / AN25
P26 / A6 ( / D6 ) / AN26
P27 / A7 ( / D7 ) / AN27
P30 / A8 ( MA0 ) ( / D8 )
P31 / A9 ( MA1 ) ( / D9 )
P37 / A15 ( MA7 ) ( / D15 ) 53
P33 / A11 ( MA3 ) ( / D11 )
P40 / A16 ( MA8 ) 52
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
51
P41 / A17 ( MA9 )
P15 / D13 / INT3
P16 / D14 / INT4
P14 / D12
P13 / D11
P17 / D15 / INT5
Vss
Vcc
D10 / P12 D9 / P11 D8 / P10 D7 / AN07 / P07 D6 / AN06 / P06 D5 / AN05 / P05 D4 / AN04 / P04 D3 / AN03 / P03 D2 / AN02 / P02 D1 / AN01 / P01 D0 / AN00 / P00 KI3 / AN37 / P107 KI2 / AN36 / P106 KI1 / AN35 / P105 KI0 / AN34 / P104 AN33 / P103 AN32 / P102 AN31 / P101 AVss AN30 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
10 12 13 14 15 16 17 19 20 21 23 24 25 18 22 11 1 2 3 4 5 6 7 8 9
50 49 48 47 46 45 44 43 42 41 40 39
P42 / A18 ( MA10 ) P43 / A19 ( MA11 ) P44 / CS3 / A20 (MA12) P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P50 / WRL / WR / CASL P51 / WRH / BHE / CASH P52 / RD / DW P53 / CLKOUT / BCLK / ALE P54 / HLDA / ALE P55 / HOLD P56 / ALE / RAS P57 / RDY P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64(1) P65 / CLK1 P66 / RxD1 / SCL1 / STxD1 P67 / TxD1 / SDA1 / SRxD1 P70(2, 4) P71(3, 4) P72 / TA1OUT / V / CLK2
M32C/82 GROUP
38 37 36 35 34 33 32 31 30 29 28 27 26
BYTE
RESET
Vss
CNVss
XOUT
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
IEOUT/ ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92
IEIN/ ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91
CLK3 / TB0IN / P90
VCONT / XCIN / P87
XCOUT / P86
Vcc
XIN
NMI / P85
INT2 / P84
INT1 / P83
INT0 / P82
U / TA4IN / P81
BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80
ISCLK0 / OUTC01 / INPC01 / TA3IN / P77
BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76
BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75
ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74
NOTES: 1. P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2 2. P70 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20 / ISTxD2 / IEOUT 3. P71 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2 / OUTC22 / ISRxD2 / IEIN 4. P70 and P71 are ports for the N-channel open drain output.
100P6Q-A
Figure 1.6 Pin Assignment for 100-Pin Package
Rev.1.20 Jun. 01, 2004 page 13
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BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
M32C/82 Group
1. Overview
Table 1.5 Pin Characteristics for 100-Pin Package
Package Pin No
FP GP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 99 100 1 2
Control pin
Port P96 P95 P94 P93 P92
Interrupt pin
Timer pin
UART pin TxD4/SDA4/SRxD4
Intelligent I/O pin
Analog pin ANEX1 ANEX0 DA1 DA0
Bus control pin
3 P91 4 P90 5 6 BYTE 7 CNVSS 8 XCIN/VCONT P87 P86 9 XCOUT 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 RESET XOUT VSS XIN VCC P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 NMI INT2 INT1 INT0
TB4IN TB3IN TB2IN TB1IN TB0IN
CLK4 CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 OUTC20/IEOUT/ISTxD2 IEIN/ISRxD2
TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V
INPC02/ISRxD0/BE0IN INPC01/OUTC01/ISCLK0 INPC00/OUTC00/ISTxD0/BE0OUT INPC12/OUTC12/ISRxD1/BE1IN INPC11/OUTC11/ISCLK1 OUTC10/ISTxD1/BE1OUT OUTC22/ISRxD2/IEIN OUTC20/ISTxD2/IEOUT
CTS2/RTS2/SS2 CLK2 TB5IN/TA0IN RxD2/SCL2/STxD2 TA0OUT TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0
OUTC21/ISCLK2
RDY ALE/RAS HOLD HLDA/ALE CLKOUT/BCLK/ALE RD/DW WRH/BHE/CASH WRL/WR/CASL CS0/A23 CS1/A22 CS2/A21 CS3/A20(MA12)
Rev.1.20 Jun. 01, 2004 page 14 of 80
M32C/82 Group
1. Overview
Table 1.5 Pin Characteristics for 100-Pin Package (Continued)
Package pin No FP GP 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 VCC P30 VSS P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 P107 P106 P105 P104 P103 P102 P101 AVSS P100 VREF AVCC P97 RxD4/SCL4/STxD4 ADTRG AN0 KI3 KI2 KI1 KI0 AN07 AN06 AN05 AN04 AN03 AN02 AN01 AN00 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 INT5 INT4 INT3 A7(/D7) A6(/D6) A5(/D5) A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A8(MA0)(/D8) P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 A19(MA11) A18(MA10) A17(MA9) A16(MA8) A15(MA7)(/D15) A14(MA6)(/D14) A13(MA5)(/D13) A12(MA4)(/D12) A11(MA3)(/D11) A10(MA2)(/D10) A9(MA1)(/D9) Control pin Port Interrupt pin Timer pin UART pin Intelligent I/O pin Analog pin Bus control pin
Rev.1.20 Jun. 01, 2004 page 15
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M32C/82 Group
1. Overview
1.6 Pin Description
Table 1.6 Pin Description (100-Pin and 144-Pin Packages)
Symbol VCC VSS CNVSS Function Power supply input CNVSS I/O type I I I Description Apply 3.0 to 5.5 V to the VCC pins. Apply 0 V to the VSS pin. Switches processor mode. Connect this pin to VSS to start up in single-chip mode (memory expansion mode). Connect this pin to VCC to start up in microprocessor mode. ___________ The microcomputer is in a reset state when applying "L" to the RESET pin. I/O pins for the main clock oscillation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To use an external clock, input the clock to XIN and leave XOUT open. Switches the data bus in external memory space 3. The data bus is 16 bits wide when the BYTE pin is held "L" and 8 bits wide when the BYTE pin is held "H". Set to either. Connect this pin to VSS when an external bus is not used. I I I I/O Applies power supply for the A/D converter and D/A converter. Connect this pin to VCC. Applies power supply for the A/D converter and D/A converter. Connect this pin to VSS. Applies reference voltage for the A/D converter. 8-bit I/O ports in CMOS having a direction register to select input or output. Each pin is set as an input port or output port. An input port in single-chip mode can be set for a pull-up or for no pull-up in 4-bit unit by program. When these pins are used as bus control pins in memory expansion mode and microprocessor mode, internal pull-up resistor cannot be selected. Ports used D0 to D7 AN00 to AN07 P10 to P17
________ ________
____________
RESET XIN XOUT BYTE
Reset input Clock input Clock output Input to switch external data bus width
I I O I
AVCC AVSS VREF P00 to P07
Analog power supply input Analog power supply input Reference voltage input I/O port P0
Data bus Analog input pin I/O port P1
______
I/O I I/O I I/O I/O O I/O I I/O O I/O
as input ports can be set for a pull-up or for no pull-up in the modes above. Inputs and outputs data (D0 to D7) when these pins are set as the separate bus. Analog input pins for the A/D converter 8-bit I/O ports having equivalent functions to P0
______
INT3 to INT5 D8 to D15 P20 to P27 A0 to A7 A0/D0 to A7/D7 AN20 to AN27 P30 to P37 A8 to A15 A8/D8 to A15/D15 MA0 to MA7 I : Input
INT interrupt input pin Data bus I/O port P2 Address bus Address bus/data bus Analog input pin I/O port P3 Address bus Address bus/data bus Address bus O : Output
Input pins for the INT interrupt Inputs and outputs data (D8 to D15) when these pins are set as the separate bus. 8-bit I/O ports having equivalent functions to P0 Outputs 8 low-order address bits (A0 to A7). Inputs and outputs data (D0 to D7) and outputs 8 low-order address bits (A0 to A7) by time-sharing when these pins are set as the multiplexed bus. Analog input pins for A/D converter 8-bit I/O ports having equivalent functions to P0 Outputs 8 middle-order address bits (A8 to A15). Inputs and outputs data (D8 to D15) and outputs 8 middle-order address bits (A8 to A15) by time-sharing when external 16-bit data bus is set as the multiplexed bus. Outputs row addresses and column addresses by time-sharing when accessing
O
the DRAM area. I/O : Input and output
Rev.1.20 Jun. 01, 2004 page 16 of 80
M32C/82 Group
1. Overview
Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)
Symbol P40 to P47 A16 to A22, _____ A23
______ ______
Function I/O port P4 Address bus Chip-select Address bus I/O port P5 Clock output Bus control pin
I/O type I/O O O O I/O O O O O O O O O I O I
Description 8-bit I/O ports having equivalent functions to P0
______
Outputs 8 high-order address bits (A16 to A22, A23). ______ The highest-order bit (A23) inversed is also output.
_______ _______ _______ _______
CS0 to CS3 MA8 to MA12 P50 to P57 CLKOUT
________
Outputs CS0 to CS3 signals. CS0 to CS3 are chip-select signals specifying an external space. Outputs row addresses and column addresses by time-sharing when accessing the DRAM area. 8-bit I/O ports having equivalent functions to P0 Outputs the main clock divided by 8 or divided by 32 or the clock having the same frequency as the sub clock from P53.
________ _________ ______ ________ _____ _________ ________
WRL ______ WR _________ WRH
________
Outputs WRL, WRH, (WR, BHE), RD, BCLK, HLDA and ALE signals. WRL _________ _______ ______ and WRH or BHE and WR can be switched by program. ________ _________ _____ WRL, WRH and RD are selected
________
BHE _____ RD BCLK __________ HLDA
__________
The WRL signal becomes "L" by writing data to an even address in an external memory space.
_________
The WRH signal becomes "L" by writing data to an odd address in an external memory space.
_____
HOLD ALE
________
The RD pin signal becomes "L" by reading data in an external memory space. ______ ________ _____ WR, BHE and RD are selected
______
RDY
The WR signal becomes "L" by writing data to an external memory space. _____ The RD signal becomes "L" by reading data in an external memory space.
________
The BHE signal becomes "L" by accessing an odd address. ______ ________ _____ Select WR, BHE and RD for an external 8-bit data bus.
__________
While the HOLD pin is held "L", the microcomputer is placed in a hold state. _________ In a hold state, HLDA outputs a "L" signal. ALE is a signal latching the address. ________ While the RDY pin is held "L", the microcomputer is placed in a wait state.
______ ______
DW _________ CASL
_________
DRAM bus control pin
O O O O
The DW signal becomes "L" by writing data to the DRAM area. _________ _________ CASL and CASH are signals indicating a timing to latch column addresses.
_________
CASH _______ RAS P60 to P67
_________ _________
The CASL signal becomes "L" by accessing an even address. __________ The CASH signal becomes "L" by accessing an odd address.
_______
I/O port P6 UART pin
I/O I O I I/O I I/O O O I/O I
RAS is a signal latching row addresses. 8-bit I/O ports having equivalent functions to P0 I/O pins for UART0 (P60 to P63) and UART1 (P64 to P67)
CTS0, CTS1 _________ _________ RTS0, RTS1
______ ______
SS0, SS1 CLK0, CLK1 RxD0, RxD1 SCL0, SCL1 STxD0, STxD1 TxD0, TxD1 SDA0, SDA1 SRxD0, SRxD1 ISCLK2 OUTC21 I : Input Intelligent I/O pin
I/O O
ISCKL2 inputs and outputs the clock for the intelligent I/O communication function. OUTC21 outputs the clock for the waveform generating function.
O : Output
I/O : Input and output
Rev.1.20 Jun. 01, 2004 page 17
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M32C/82 Group
1. Overview
Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)
Symbol P70 to P77 Function I/O port P7 I/O type I/O I/O I I O O I O I I/O I I/O O O I/O I I O INPC00, INPC01, INPC11 and INPC12 are input pins for the time measurement function. OUTC00, OUTC01, OUTC10 to OUTC12, OUTC20 and OUTC22 are output pins for the waveform generating function. ISCLK0 and ISCLK1 input and output the clock for the intelligent I/O communiI/O O I O I O O I O : Output I/O : Input and output cation function. ISRxD1, ISRxD2, IEIN and BE1IN input received data for the intelligent I/O communication function. ISTxD0 to ISTxD2, IEOUT, BE0OUT and BE1OUT output transmit data for the intelligent I/O communication function. Description 8-bit I/O ports having equivalent functions to P0 (P70 and P71 are ports for the N-channel open drain output.) I/O pins for timer A0 to A3 Input pin for timer B5 V-phase output pin W-phase output pin I/O pins for UART2
TA0OUT to TA3OUT Timer A pin TA0IN to TA3IN TB5IN
___
V, V ___ W, W _________ CTS2
_________
Timer B pin Three-phase motor control output pin UART pin
RTS2 ______ SS2 CLK2 RxD2 SCL2 STxD2 TxD2 SDA2 SRxD2 INPC00, INPC01 Intelligent I/O pin INPC11, INPC12 OUTC00, OUTC01 OUTC10 to OUTC12 OUTC20, OUTC22 ISCLK0, ISCLK1 ISTxD0 to ISTxD2 ISRxD1, ISRxD2 IEOUT IEIN BE0OUT BE1OUT BE1IN I : Input
Rev.1.20 Jun. 01, 2004 page 18 of 80
M32C/82 Group
1. Overview
Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)
Symbol P80 to P84, P86, P87 XCIN XCOUT VCONT Function I/O port P8 Sub clock Low-pass filter connect pin for PLL frequency synthesizer pin TA4OUT TA4IN
___
I/O type I/O I O
Description I/O ports having equivalent functions to P0 I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT. Connects the low-pass filter to the VCONT pin when using the PLL frequency synthesizer. Connect P86 to VSS to stabilize the PLL frequency.
Timer A pin Three-phase motor control output pin
________ ______
I/O I O I I I I I I/O I I O I I/O I I/O O O I/O I O I/O I I O O O I I
I/O pins for timer A4 U-phase output pins
______
U, U
________
INT0 to INT2 INPC02 ISRxD0 BE0IN
_______
INT interrupt input pin Intelligent I/O pin
Input pins for the INT interrupt INPC02 is an input pin for the time measurement function. ISRxD0 and BE0IN input received data for the intelligent I/O communication function.
_______
_______
P85/NMI P90 to P97
NMI interrupt input pin I/O port P9
Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register. 8-bit I/O ports having equivalent functions P0. The PRCR register prevents PD9 and PS3 registers from rewriting. Input pins for timers B0 to B4 I/O pins for UART3 (P90 to P93) and UART4 (P94 to P97)
TB0IN to TB4IN Timer B pin _________ __________ CTS3, CTS4 UART pin _________ _________ RTS3, RTS4 _______ _______ SS3, SS4 CLK3, CLK4 RxD3, RxD4 SCL3, SCL4 STxD3, STxD4 TxD3, TxD4 SDA3, SDA4 SRxD3, SRxD4 DA0, DA1 D/A output pin ANEX0, ANEX1,
___________
Output pins for the D/A converter ANEX0 is an extended analog I/O pin for the A/D converter. ANEX1 is an extended analog input pin for the A/D converter.
__________
A/D related pin
ADTRG OUTC20 ISTxD2 IEOUT IEIN ISRxD2 P100 to P107
_____ _____
Intelligent I/O pin
ADTRG is an A/D trigger input pin. OUTC20 is an output pin for the waveform generating function. ISTxD2 and IEOUT output transmit data for the intelligent I/O communication function. ISRxD2 and IEIN input received data for the intelligent I/O communication function. 8-bit I/O ports having equivalent functions to P0 Input pins for the key input interrupt Analog input pins for the A/D converter
KI0 to KI3 AN0 to AN7 I : Input
I/O port P10 Key input interrupt pin Analog input pin
I/O I I
O : Output
I/O : Input and output
Rev.1.20 Jun. 01, 2004 page 19
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M32C/82 Group
1. Overview
Table 1.6 Pin Description (144-Pin Package only) (Continued)
Symbol Function I/O type I/O I O I/O I I O O I/O I/O O I/O I I O O I/O I O I/O I O I/O I I O O I Description 5-bit I/O ports having equivalent functions to P0. INPC11 and INPC12 are input pins for the time measurement function. OUTC10 to OUTC13 are output pins for the waveform generating function. ISCLK1 inputs and outputs the clock for the intelligent I/O communication function. ISRxD1 and BE1IN input received data for the intelligent I/O communication function. ISTxD1 and BE1OUT output transmit data for the intelligent I/O communication function. 8-bit I/O ports having equivalent functions to P0 8-bit I/O ports having equivalent functions to P0 OUTC20 to OUTC27 are output pins for the waveform generating function. ISCLK2 inputs and outputs the clock for the intelligent I/O communication function. ISRxD2 and IEIN input received data for the intelligent I/O communication function. ISTxD2 and IEOUT output transmit data for the intelligent I/O communication function. 7-bit I/O ports having equivalent functions to P0 INPC16 and INPC17 are input pins for the time measurement function. OUTC14 to OUTC17 are output pins for the waveform generating function. 8-bit I/O ports having equivalent functions to P0 INPC00 to INPC07 are input pins for the time measurement function. OUTC00, OUTC01, OUTC04 and OUTC05 are output pins for the waveform generating function. ISCLK0 inputs and outputs the clock for the intelligent I/O communication function. ISRxD0 and BE0IN input received data for the intelligent I/O communication function. ISTxD0 and BE0OUT output transmit data for the intelligent I/O communication function. Analog input pins for the A/D converter I/O port P11 P110 to P114 INPC11, INPC12 Intelligent I/O pin OUTC10 to OUTC13 ISCLK1 ISRxD1 BE1IN ISTxD1 BE1OUT P120 to P127 I/O port P12 I/O port P13 P130 to P137 OUTC20 to OUTC27 Intelligent I/O pin ISCLK2 ISRxD2 IEIN ISTxD2 IEOUT I/O port P14 P140 to P146 INPC16, INPC17 Intelligent I/O pin OUTC14 to OUTC17 P150 to P157 I/O port P15 INPC00 to INPC07 Intelligent I/O pin OUTC00, OUTC01 OUTC04, OUTC05 ISCLK0 ISRxD0 BE0IN ISTxD0 BE0OUT AN150 to AN157 Analog input port I : Input O : Output
I/O : Input and output
Rev.1.20 Jun. 01, 2004 page 20 of 80
M32C/82 Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. A register bank comprises 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers. Two sets of register banks are provided.
b31
b15
b0
General register
R2 R3
R0H R1H R2
R0L R1L Data register(1)
b23
R3 A0 A1 SB FB USP ISP INTB PC FLG Address register(1) Static base register(1) Frame base register(1) User stack pointer Interrupt stack pointer Interrupt table register Program counter Flag register
b0
b15
b8 b7
IPL
U I OBSZDC
Carry flag Debug flag Zero flag Sign flag Register bank flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved space Processor interrupt priority level Reserved space
b15 b0
High-speed interrupt register
b23
SVF SVP VCT
b7 b0
Flag save register PC save register Vector register
DMAC related register
b15
DMD0 DMD1 DCT0 DCT1 DRC0
b23
DMA mode register
DMA transfer count register
DRC1 DMA0 DMA1 DRA0 DRA1 DSA0 DSA1
DMA transfer count reload register
DMA memory address register
DMA memory address reload register
DMA SFR adress register
NOTES: 1. A register bank comprise these registers. Two sets of register banks are provided.
Figure 2.1 CPU Register
Rev.1.20 Jun. 01, 2004 page 21
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M32C/82 Group
2. Central Processing Unit (CPU)
2.1 General Register 2.1.1 Data Registers (R0, R1, R2 and R3)
R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R3R1.
2.1.2 Address Registers (A0 and A1)
A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations.
2.1.3 Static Base Register (SB)
SB is a 24-bit register for SB-relative addressing.
2.1.4 Frame Base Register (FB)
FB is a 24-bit register for FB-relative addressing.
2.1.5 Program Counter (PC)
PC is 24 bits wide. It indicates an address of an instruction to be executed.
2.1.6 Interrupt Table Register (INTB)
INTB is a 24-bit register indicating a starting address of an interrupt vector table.
2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
USP and ISP as the stack pointer are 24 bits wide. The U flag can switch USP to ISP and vice versa. Refer to "2.1.8 Flag Register (FLG)" about the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently.
2.1.8 Flag Register (FLG)
FLG is a 16-bit register indicating a CPU state. 2.1.8.1 Carry Flag (C) The C flag indicates whether carry or borrow occurs after an instruction is executed. 2.1.8.2 Debug Flag (D) The D flag is for debug only. Set to "0". 2.1.8.3 Zero Flag (Z) The Z flag is set to "1" when the value of zero is obtained from an arithmetic calculation; otherwise "0". 2.1.8.4 Sign Flag (S) The S flag is set to "1" when a negative value is obtained from an arithmetic calculation; otherwise "0".
Rev.1.20 Jun. 01, 2004 page 22
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M32C/82 Group
2. Central Processing Unit (CPU)
2.1.8.5 Register Bank Select Flag (B) The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this flag is set to "1". 2.1.8.6 Overflow Flag (O) The O flag is set to "1" when a result of an arithmetic operation overflows; otherwise "0". 2.1.8.7 Interrupt Enable Flag (I) The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to "0" and is enabled when the I flag is set to "1". The I flag is set to "0" when an interrupt is acknowledged. 2.1.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1". The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.1.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide. It assigns an interrupt priority levels from level 0 to level 7. If a requested interrupt has a greater priority than IPL, the interrupt is enabled. 2.1.8.10 Reserved Space When writing to the reserved space, set to "0". When read, its content is indeterminate.
2.2 High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are as follows. - Flag save register (SVF) - PC save register (SVP) - Vector register (VCT)
2.3 DMAC-associated Registers
Registers associated with DMAC are as follows. - DMA mode register (DMD0, DMD1) - DMA transfer count register (DCT0, DCT1) - DMA transfer count reload register (DRC0, DRC1) - DMA memory address register (DMA0, DMA1) - DMA SFR address register (DSA0, DSA1) - DMA memory address reload register (DRA0, DRA1)
Rev.1.20 Jun. 01, 2004 page 23
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M32C/82 Group
3. Memory
3. Memory
Figure 3.1 shows a memory map of the M32C/82 group. The M32C/82 provides 16-Mbyte address space from addresses 00000016 to FFFFFF16. The internal ROM is allocated in lower addresses beginning with address FFFFFF16. For example, a 64Kbyte internal ROM is allocated in addresses FF000016 to FFFFFF16. The fixed interrupt vectors are allocated in addresses FFFFDC16 to FFFFFF16. It stores the starting address of each interrupt routine. The internal RAM is allocated in higher addresses beginning with address 00040016. For example, a 10Kbyte internal RAM is allocated in addresses 00040016 to 002BFF16. Besides storing data, it becomes stacks when the subroutine is called or an interrupt is acknowleged. The SFR is allocated in addresses 00000016 to 0003FF16. The control registers for peripheral functions such as I/O port, A/D conversion, serial I/O, timer are allocated here. All addresses, which have nothing allocated within the SFR, are reserved space and cannot be accessed by users. The special page vectors are allocated in addresses FFFE0016 to FFFFDB16. It is used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication Software Manual for details. In memory expansion mode and microprocessor mode, some space are reserved and cannot be accessed by users.
00000016 SFR 00040016 XXXXXX16 00800016 Internal RAM Reserved space(1) FFFE0016 Special page vector table External space FFFFDC16 Undefined instruction Overflow BRK instruction Address match F0000016 YYYYYY16 Internal RAM FA000016 007FFF16 FFFFFF16 FFFFFF16 Reserved space(2) Watchdog timer NMI Reset
Type number M30823MW M30825MW M30823MH M30825MH M30826MH M30828MH
Address
XXXXXX16
Address YYYYYY16 FB000016
0063FF16
NOTES: 1. In memory expansion and microprocessor modes 2. In memory expansion mode
Figure 3.1 Memory Map
Rev.1.20 Jun. 01, 2004 page 24 of 80
M32C/82 Group
3. Special Function Registers (SFR)
4. Special Function Registers (SFR)
Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 Register Symbol Value after RESET
1000 00002 (CNVss pin ="L") Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Wait control register Address match interrupt enable register Protect register External data bus width control register Main clock division register Oscillation stop detect register Watchdog timer start register Watchdog timer control register Address match interrupt register 0 PM0 PM1 CM0 CM1 WCR AIER PRCR DS MCD CM2 WDTS WDC RMAD0 0000 00112 (CNVss pin ="H") 0X00 00002 0000 X0002 0010 00002 1111 11112 XXXX 00002 XXXX 00002 XXXX 10002 (BYTE pin ="L") XXXX 00002 (BYTE pin ="H") XXX0 10002 0016 XX16 000X XXXX2 00000016
Address match interrupt register 1 VDC control register for PLL Address match interrupt register 2 VDC control register 0 Address match interrupt register 3
RMAD1 PLV RMAD2 VDC0 RMAD3
00000016 XXXX XX012 00000016 0016 00000016
X: Indeterminate Blank spaces are reserved. No access is allowed.
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M32C/82 Group
3. Special Function Registers (SFR)
Address Register 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 DRAM control register 004116 DRAM refresh interval set register 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16
Symbol
Value after RESET
DRAMCONT REFCNT
XX16 XX16
X: Indeterminate Blank spaces are reserved. No access is allowed.
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M32C/82 Group
3. Special Function Registers (SFR)
Address 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16
Register
Symbol
Value after RESET
DMA0 interrupt control register Timer B5 interrupt control register DMA2 interrupt control register UART2 receive /ACK interrupt control register Timer A0 interrupt control register UART3 receive /ACK interrupt control register Timer A2 interrupt control register UART4 receive /ACK interrupt control register Timer A4 interrupt control register UART0/UART3 bus conflict detect interrupt control register UART0 receive/ACK interrupt control register A/D0 conversion interrupt control register UART1 receive/ACK interrupt control register Intelligent I/O interrupt control register 0 Timer B1 interrupt control register Intelligent I/O interrupt control register 2 Timer B3 interrupt control register Intelligent I/O interrupt control register 4 INT5 interrupt control register Intelligent I/O interrupt control register 6 INT3 interrupt control register Intelligent I/O interrupt control register 8 INT1 interrupt control register Intelligent I/O interrupt control register 10 Intelligent I/O interrupt control register 11
DM0IC TB5IC DM2IC S2RIC TA0IC S3RIC TA2IC S4RIC TA4IC BCN0IC/BCN3IC S0RIC AD0IC S1RIC IIO0IC TB1IC IIO2IC TB3IC IIO4IC INT5IC IIO6IC INT3IC IIO8IC INT1IC IIO10IC IIO11IC
XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XX00 X0002 XXXX X0002 XX00 X0002 XXXX X0002 XX00 X0002 XXXX X0002 XXXX X0002
DMA1 interrupt control register UART2 transmit /NACK interrupt control register DMA3 interrupt control register UART3 transmit /NACK interrupt control register Timer A1 interrupt control register UART4 transmit /NACK interrupt control register Timer A3 interrupt control register UART2 bus conflict detect interrupt control register
DM1IC S2TIC DM3IC S3TIC TA1IC S4TIC TA3IC BCN2IC
XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002
X: Indeterminate Blank spaces are reserved. No access is allowed.
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M32C/82 Group
3. Special Function Registers (SFR)
Address 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16
Register UART0 transmit /NACK interrupt control register UART1/UART4 bus conflict detect interrupt control register UART1 transmit/NACK interrupt control register Key input interrupt control register Timer B0 interrupt control register Intelligent I/O interrupt control register 1 Timer B2 interrupt control register Intelligent I/O interrupt control register 3 Timer B4 interrupt control register Intelligent I/O interrupt control register 5 INT4 interrupt control register Intelligent I/O interrupt control register 7 INT2 interrupt control register Intelligent I/O interrupt control register 9 INT0 interrupt control register Exit priority control register Interrupt request register 0 Interrupt request register 1 Interrupt request register 2 Interrupt request register 3 Interrupt request register 4 Interrupt request register 5 Interrupt request register 6 Interrupt request register 7 Interrupt request register 8 Interrupt request register 9 Interrupt request register 10 Interrupt request register 11
Symbol S0TIC BCN1IC/BCN4IC S1TIC KUPIC TB0IC IIO1IC TB2IC IIO3IC TB4IC IIO5IC INT4IC IIO7IC INT2IC IIO9IC INT0IC RLVL IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR IIO5IR IIO6IR IIO7IR IIO8IR IIO9IR IIO10IR IIO11IR
Value after RESET XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XX00 X0002 XXXX X0002 XX00 X0002 XXXX X0002 XX00 X0002 XXXX 00002 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2
Interrupt enable register 0 Interrupt enable register 1 Interrupt enable register 2 Interrupt enable register 3 Interrupt enable register 4 Interrupt enable register 5 Interrupt enable register 6 Interrupt enable register 7 Interrupt enable register 8 Interrupt enable register 9 Interrupt enable register 10 Interrupt enable register 11
IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE IIO5IE IIO6IE IIO7IE IIO8IE IIO9IE IIO10IE IIO11IE
0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016
X: Indeterminate Blank spaces are reserved. No access is allowed.
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M32C/82 Group
3. Special Function Registers (SFR)
Address 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16
Register Group 0 time measurement/waveform generating register 0 Group 0 time measurement/waveform generating register 1 Group 0 time measurement/waveform generating register 2 Group 0 time measurement/waveform generating register 3 Group 0 time measurement/waveform generating register 4 Group 0 time measurement/waveform generating register 5 Group 0 time measurement/waveform generating register 6 Group 0 time measurement/waveform generating register 7 Group 0 waveform generating control register 0 Group 0 waveform generating control register 1 Group 0 waveform generating control register 2 Group 0 waveform generating control register 3 Group 0 waveform generating control register 4 Group 0 waveform generating control register 5 Group 0 waveform generating control register 6 Group 0 waveform generating control register 7 Group 0 time measurement control register 0 Group 0 time measurement control register 1 Group 0 time measurement control register 2 Group 0 time measurement control register 3 Group 0 time measurement control register 4 Group 0 time measurement control register 5 Group 0 time measurement control register 6 Group 0 time measurement control register 7 Group 0 base timer register Group 0 base timer control register 0 Group 0 base timer control register 1 Group 0 time measurement prescaler register 6 Group 0 time measurement prescaler register 7 Group 0 function enable register Group 0 function select register Group 0 SI/O receive buffer register Group 0 transmit buffer/receive data register Group 0 receive input register Group 0 SI/O communication mode register Group 0 transmit output register Group 0 SI/O communication control register
Symbol G0TM0/G0PO0 G0TM1/G0PO1 G0TM2/G0PO2 G0TM3/G0PO3 G0TM4/G0PO4 G0TM5/G0PO5 G0TM6/G0PO6 G0TM7/G0PO7 G0POCR0 G0POCR1 G0POCR2 G0POCR3 G0POCR4 G0POCR5 G0POCR6 G0POCR7 G0TMCR0 G0TMCR1 G0TMCR2 G0TMCR3 G0TMCR4 G0TMCR5 G0TMCR6 G0TMCR7 G0BT G0BCR0 G0BCR1 G0TPR6 G0TPR7 G0FE G0FS G0RB G0TB/G0DR G0RI G0MR G0TO G0CR
Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0016 0016 0016 0016 0016 0016 0016 0016 XX16 XX16 0016 0016 0016 0016 0016 0016 XXXX XXXX2 XX00 XXXX2 XX16 XX16 0016 XX16 0000 X0002
X: Indeterminate Blank spaces are reserved. No access is allowed.
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M32C/82 Group
3. Special Function Registers (SFR)
Address 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 011816 011916 011A16 011B16 011C16 011D16 011E16 011F16
Register Group 0 data compare register 0 Group 0 data compare register 1 Group 0 data compare register 2 Group 0 data compare register 3 Group 0 data mask register 0 Group 0 data mask register 1
Symbol G0CMP0 G0CMP1 G0CMP2 G0CMP3 G0MSK0 G0MSK1
Value after RESET XX16 XX16 XX16 XX16 XX16 XX16
XX16 Group 0 receive CRC code register Group 0 transmit CRC code register Group 0 SI/O extended mode register Group 0 SI/O extended receive control register Group 0 SI/O special communication interrupt detect register Group 0 SI/O extended transmit control register Group 1 time measurement/waveform generating register 0 Group 1 time measurement/waveform generating register 1 Group 1 time measurement/waveform generating register 2 Group 1 time measurement/waveform generating register 3 Group 1 time measurement/waveform generating register 4 Group 1 time measurement/waveform generating register 5 Group 1 time measurement/waveform generating register 6 Group 1 time measurement/waveform generating register 7 Group 1 waveform generating control register 0 Group 1 waveform generating control register 1 Group 1 waveform generating control register 2 Group 1 waveform generating control register 3 Group 1 waveform generating control register 4 Group 1 waveform generating control register 5 Group 1 waveform generating control register 6 Group 1 waveform generating control register 7 Group 1 time measurement control register 0 Group 1 time measurement control register 1 Group 1 time measurement control register 2 Group 1 time measurement control register 3 Group 1 time measurement control register 4 Group 1 time measurement control register 5 Group 1 time measurement control register 6 Group 1 time measurement control register 7 G0RCRC G0TCRC G0EMR G0ERC G0IRF G0ETC G1TM0/G1PO0 G1TM1/G1PO1 G1TM2/G1PO2 G1TM3/G1PO3 G1TM4/G1PO4 G1TM5/G1PO5 G1TM6/G1PO6 G1TM7/G1PO7 G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 XX16 0016 0016 0016 0016 0000 00XX2 0000 0XXX2 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0016 0016 0016 0016 0016 0016 0016 0016
X: Indeterminate Blank spaces are reserved. No access is allowed.
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M32C/82 Group
3. Special Function Registers (SFR)
Address 012016 012116 012216 012316 012416 012516 012616 012716 012816 012916 012A16 012B16 012C16 012D16 012E16 012F16 013016 013116 013216 013316 013416 013516 013616 013716 013816 013916 013A16 013B16 013C16 013D16 013E16 013F16 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A16 014B16 014C16 014D16 014E16 014F16
Register Group 1 base timer register Group 1 base timer control register 0 Group 1 base timer control register 1 Group 1 time measurement prescaler register 6 Group 1 time measurement prescaler register 7 Group 1 function enable register Group 1 function select register Group 1 SI/O receive buffer register Group 1 transmit buffer/receive data register Group 1 receive input register Group 1 SI/O communication mode register Group 1 transmit output register Group 1 SI/O communication control register Group 1 data compare register 0 Group 1 data compare register 1 Group 1 data compare register 2 Group 1 data compare register 3 Group 1 data mask register 0 Group 1 data mask register 1
Symbol G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS G1RB G1TB/G1DR G1RI G1MR G1TO G1CR G1CMP0 G1CMP1 G1CMP2 G1CMP3 G1MSK0 G1MSK1
Value after RESET XX16 XX16 0016 0016 0016 0016 0016 0016 XXXX XXXX2 XX00 XXXX2 XX16 XX16 0016 XX16 0000 X0002 XX16 XX16 XX16 XX16 XX16 XX16
XX16 Group 1 receive CRC code register Group 1 transmit CRC code register Group 1 SI/O extended mode register Group 1 SI/O extended receive control register Group 1 SI/O special communication interrupt detect register Group 1 SI/O extended transmit control register Group 2 waveform generating register 0 Group 2 waveform generating register 1 Group 2 waveform generating register 2 Group 2 waveform generating register 3 Group 2 waveform generating register 4 Group 2 waveform generating register 5 Group 2 waveform generating register 6 Group 2 waveform generating register 7 G1RCRC G1TCRC G1EMR G1ERC G1IRF G1ETC G2PO0 G2PO1 G2PO2 G2PO3 G2PO4 G2PO5 G2PO6 G2PO7 XX16 0016 0016 0016 0016 0000 00XX2 0000 0XXX2 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16
X: Indeterminate Blank spaces are reserved. No access is allowed.
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M32C/82 Group
3. Special Function Registers (SFR)
Address 015016 015116 015216 015316 015416 015516 015616 015716 015816 015916 015A16 015B16 015C16 015D16 015E16 015F16 016016 016116 016216 016316 016416 016516 016616 016716 016816 016916 016A16 016B16 016C16 016D16 016E16 016F16 017016 017116 017216 017316 017416 017516 017616 017716 017816 017916 017A16 to 01D316 01D416 01D516 01D616 01D716 01D816 to 02BF16
Register Group 2 waveform generating control register 0 Group 2 waveform generating control register 1 Group 2 waveform generating control register 2 Group 2 waveform generating control register 3 Group 2 waveform generating control register 4 Group 2 waveform generating control register 5 Group 2 waveform generating control register 6 Group 2 waveform generating control register 7
Symbol G2POCR0 G2POCR1 G2POCR2 G2POCR3 G2POCR4 G2POCR5 G2POCR6 G2POCR7
Value after RESET 0016 0016 0016 0016 0016 0016 0016 0016
XX16 Group 2 base timer register Group 2 base timer control register 0 Group 2 base timer control register 1 Base timer start register Group 2 function enable register Group 2 RTP output buffer register G2BT G2BCR0 G2BCR1 BTSR G2FE G2RTP XX16 0016 0016 XXXX 00002 0016 0016
Group 2 SI/O communication mode register Group 2 SI/O communication control register Group 2 SI/O transmit buffer register Group 2 SI/O receive buffer register Group 2 IEBus address register Group 2 IEBus control register Group 2 IEBus transmit interrupt cause detect register Group 2 IEBus receive interrupt cause detect register
G2MR G2CR G2TB G2RB IEAR IECR IETIF IERIF
00XX X0002 0000 X0002 XX16 XX16 XX16 XX16 XX16 XX16 00XX X0002 XXX0 00002 XXX0 00002
Input function select register
IPS
0016
A/D1 control register 2 A/D1 control register 0 A/D1 control register 1
AD1CON2 AD1CON0 AD1CON1
X00X X0002 0016 XX00 00002
X: Indeterminate Blank spaces are reserved. No access is allowed.
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3. Special Function Registers (SFR)
Address 02C016 02C116 02C216 02C316 02C416 02C516 02C616 02C716 02C816 02C916 02CA16 02CB16 02CC16 02CD16 02CE16 02CF16 02D016 02D116 02D216 02D316 02D416 02D516 02D616 02D716 02D816 02D916 02DA16 02DB16 02DC16 02DD16 02DE16 02DF16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16 X0 register Y0 register X1 register Y1 register X2 register Y2 register X3 register Y3 register X4 register Y4 register X5 register Y5 register X6 register Y6 register X7 register Y7 register X8 register Y8 register X9 register Y9 register
Register
Symbol X0R,Y0R X1R,Y1R X2R,Y2R X3R,Y3R X4R,Y4R X5R,Y5R X6R,Y6R X7R,Y7R X8R,Y8R X9R,Y9R X10R,Y10R X11R,Y11R X12R,Y12R X13R,Y13R X14R,Y14R X15R,Y15R XYC
Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XXXX XX002
X10 register Y10 register X11 register Y11 register X12 register Y12 register X13 register Y13 register X14 register Y14 register X15 register Y15 register XY control register
UART1 special mode register 4 UART1 special mode register 3 UART1 special mode register 2 UART1 special mode register UART1 transmit/receive mode register UART1 baud rate register
U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB
0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16
UART1 transmit buffer register 02EB16 02EC16 UART1 transmit/receive control register 0 02ED16 UART1 transmit/receive control register 1 02EE16 UART1 receive buffer register 02EF16
X: Indeterminate Blank spaces are reserved. No access is allowed.
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3. Special Function Registers (SFR)
Address 02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA16 02FB16 02FC16 02FD16 02FE16 02FF16 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16
Register
Symbol
Value after RESET
UART4 special mode register 4 UART4 special mode register 3 UART4 special mode register 2 UART4 special mode register UART4 transmit/receive mode register UART4 baud rate register UART4 transmit buffer register UART4 transmit/receive control register 0 UART4 transmit/receive control register 1 UART4 receive buffer register Timer B3,B4,B5 count start flag
U4SMR4 U4SMR3 U4SMR2 U4SMR U4MR U4BRG U4TB U4C0 U4C1 U4RB TBSR
0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16 000X XXXX2 XX16
Timer A1-1 register Timer A2-1 register Timer A4-1 register Three-phase PWM control register 0 Three-phase PWM control register 1 Three-phase output buffer register 0 Three-phase output buffer register 1 Dead time timer Timer B2 interrupt generating frequency set counter
TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2
XX16 XX16 XX16 XX16 XX16 0016 0016 XX11 11112 XX11 11112 XX16 XX16
XX16 Timer B3 register Timer B4 register Timer B5 register TB3 TB4 TB5 XX16 XX16 XX16 XX16 XX16
Timer B3 mode register Timer B4 mode register Timer B5 mode register External interrupt cause select register
TB3MR TB4MR TB5MR IFSR
00XX 00002 00XX 00002 00XX 00002 0016
X: Indeterminate Blank spaces are reserved. No access is allowed.
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M32C/82 Group
3. Special Function Registers (SFR)
Address 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16
Register
Symbol
Value after RESET
UART3 special mode register 4 UART3 special mode register 3 UART3 special mode register 2 UART3 special mode register UART3 transmit/receive mode register UART3 baud rate register UART3 transmit buffer register UART3 transmit/receive control register 0 UART3 transmit/receive control register 1 UART3 receive buffer register
U3SMR4 U3SMR3 U3SMR2 U3SMR U3MR U3BRG U3TB U3C0 U3C1 U3RB
0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16
UART2 special mode register 4 UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register UART2 transmit/receive mode register UART2 baud rate register UART2 transmit buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register Count start flag Clock prescaler reset flag One-shot start flag Trigger select register Up-down flag
U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR CPSRF ONSF TRGSR UDF
0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16 0016 0XXX XXXX2 0016 0016 0016 XX16
Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register
TA0 TA1 TA2 TA3 TA4
XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16
X: Indeterminate Blank spaces are reserved. No access is allowed.
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M32C/82 Group
3. Special Function Registers (SFR)
Address Register 035016 Timer B0 register 035116 035216 Timer B1 register 035316 035416 Timer B2 register 035516 035616 Timer A0 mode register 035716 Timer A1 mode register 035816 Timer A2 mode register 035916 Timer A3 mode register 035A16 Timer A4 mode register 035B16 Timer B0 mode register 035C16 Timer B1 mode register 035D16 Timer B2 mode register 035E16 Timer B2 special mode register 035F16 Count source prescaler register 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16
Symbol TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC TCSPR
Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 0000 0X002 0000 0X002 0000 0X002 0000 0X002 0000 0X002 00XX 00002 00XX 00002 00XX 00002 XXXX XXX02 0XXX 00002
UART0 special mode register 4 UART0 special mode register 3 UART0 special mode register 2 UART0 special mode register UART0 transmit/receive mode register UART0 baud rate register UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register
U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB
0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16
PLL control register 0 PLL control register 1 DMA0 cause select register DMA1 cause select register DMA2 cause select register DMA3 cause select register CRC data register CRC input register
PLC0 PLC1 DM0SL DM1SL DM2SL DM3SL CRCD CRCIN
0011 X1002 XXXX 00002 0X00 00002 0X00 00002 0X00 00002 0X00 00002 XX16 XX16 XX16
X: Indeterminate Blank spaces are reserved. No access is allowed.
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3. Special Function Registers (SFR)
Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 A/D0 register 0 A/D0 register 1 A/D0 register 2 A/D0 register 3 A/D0 register 4 A/D0 register 5 A/D0 register 6 A/D0 register 7
Register
Symbol AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07
Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16
A/D0 control register 2 A/D0 control register 0 A/D0 control register 1 D/A register 0 D/A register 1 D/A control register
AD0CON2 AD0CON0 AD0CON1 DA0 DA1 DACON
X000 00002 0016 0016 XX16 XX16 XXXX XX002
X: Indeterminate Blank spaces are reserved. No access is allowed.
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M32C/82 Group
3. Special Function Registers (SFR)
<144-pin package>
Address 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 Register Function select register A8 Function select register A9 Symbol PS8 PS9 Value after RESET X000 00002 0016
Function select register C Function select register A0 Function select register A1 Function select register B0 Function select register B1 Function select register A2 Function select register A3 Function select register B2 Function select register B3 Function select register A5
PSC PS0 PS1 PSL0 PSL1 PS2 PS3 PSL2 PSL3 PS5
00X0 00002 0016 0016 0016 0016 00X0 00002 0016 00X0 00002 0016 XXX0 00002
Function select register A7
PS7
0016
Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register Port P11 register Port P10 direction register Port P11 direction register Port P12 register Port P13 register Port P12 direction register Port P13 direction register
P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13
XX16 XX16 0016 0016 XX16 XX16 00X0 00002 0016 XX16 XX16 0016 XXX0 00002 XX16 XX16 0016 0016
X: Indeterminate Blank spaces are reserved. No access is allowed.
Rev.1.20 Jun. 01, 2004 page 38
of 80
M32C/82 Group
3. Special Function Registers (SFR)
<144-pin package>
Address 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Register Port P14 register Port P15 register Port P14 direction register Port P15 direction register Symbol P14 P15 PD14 PD15 Value after RESET XX16 XX16 X000 00002 0016
Pull-up control register 2 Pull-up control register 3 Pull-up control register 4
PUR2 PUR3 PUR4
0016 0016 XXXX 00002
Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5
XX16 XX16 0016 0016 XX16 XX16 0016 0016 XX16 XX16 0016 0016
Pull-up control register 0 Pull-up control register 1
PUR0 PUR1
0016 XXXX 00002
Port control register
PCR
XXXX XXX02
X: Indeterminate Blank spaces are reserved. No access is allowed.
Rev.1.20 Jun. 01, 2004page 39
of 80
1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
1 19 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 4037251300988674615947343212009785736098463421192714329280776553409826140199877432524037251309886746159473221 1 98 6 4 219 7 5 32 0 8 652 1 1 98 6 4 215 7 5 32 0 8 650 1 1 98 6 4 213 7 5 32 0 8 656 1 1 98 6 4 2109 7 5 32 0 8 6543 1 8 6 4 21 403725130098867461594734321200978573609846342119271432928077655340982614019987743252403725130098867461594734321 9 7 5 32 0 8 652 1 1 98 6 4 215 7 5 32 0 8 650 1 1 98 6 4 213 7 5 32 0 8 656 1 1 98 6 4 219 7 5 32 0 8 652 43210987654321098765432121098765432109876543210987654321 403725130098867461594734321200978573609846342119271432928077655340982614019987743252403725130098867461594734321 9 7 5 32 0 8 652 1 1 98 6 4 215 7 5 32 0 8 650 1 1 98 6 4 213 7 5 32 0 8 656 1 1 98 6 4 219 7 5 32 0 8 652 1 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 98 6 4 21 109 1 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432
43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321
Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 XX16 XX16 0016 0016 XX16 XX16 00X0 00002 0016 XX16
43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 1 43210987654321098765432121098765432109876543210987654321 4321098765432109876543212109876543210987654321098765432 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321
Function select register B0 Function select register B1 Function select register A2 Function select register A3 Function select register B2 Function select register B3 PSL0 PSL1 PS2 PS3 PSL2 PSL3 0016 0016 00X0 00002 0016 00X0 00002 0016
M32C/82 Group
Address 03A016 03A116 03A216 03A316 03A416
43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321
Register Symbol Value after RESET
Rev.1.20 Jun. 01, 2004 page 40
7654321 7654321 7654321 7654321
Blank spaces are reserved. No access is allowed. NOTES:
X: Indeterminate
03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16
03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 Function select register C 03B016 Function select register A0 03B116 Function select register A1
<100-pin package>
1. 2.
the 100-pin package.
Port P10 direction register
Set address spaces 03CB16, 03CE16 and 03CF16 to "FF16" in the 100-pin package. Address spaces 03A016, 03A116, 03B916, 03BC16, 03BD16, 03C916, 03CC16 and 03CD16 are not provided in
of 80
PD10 PSC PS0 PS1
4321 4321
3. Special Function Registers (SFR)
0016
0X00 00002 0016 0016
(Note 1) (Note 2) (Note 1) (Note 2) (Note 2) (Note 2) (Note 2)
65432109876543212109876543210987654321098765432121098765432109876543210987654321 65432109876543212109876543210987654321098765432121098765432109876543210987654321 65432109876543212109876543210987654321098765432121098765432109876543210987654321
Pull-up control register 2 Pull-up control register 3 PUR2 PUR3 0016 0016
098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
M32C/82 Group
Address 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16
0 87 5 3 10 098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 4936241209878573605846332111099684726987453320182613219189766452498725130098867321514936241209785736058463211 9 6 4 21 9 7 542 2 0 87 5 3 105 6 4 21 9 7 540 2 0 87 5 3 103 6 4 21 9 7 546 2 0 87 5 3 1098 6 4 21 9 7 5432 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321
Rev.1.20 Jun. 01, 2004page 41
4321 44321 32 54 21 54321 5543211 63
654321 654321
Blank spaces are reserved. No access is allowed. NOTES:
X: Indeterminate
<100-pin package>
1. 2.
3.
Port control register
Pull-up control register 0 Pull-up control register 1
Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register
Set address spaces 03D216 and 03D316 to "FF16" in the 100-pin package. Set address spaces 03DC16 to "0016" in the 100-pin package.
Address spaces 03D016 and 03D116 are not provided in the 100-pin package.
of 80
Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 PCR PUR0 PUR1 Symbol
3. Special Function Registers (SFR)
Value after RESET
XX16 XX16 0016 0016 XX16 XX16 0016 0016 XX16 XX16 0016 0016
XXXX XXX02 0016 XXXX 00002
(Note 2) (Note 1) (Note 3)
M32C/82 Group
5. Electrical Characteristics
5. Electrical Characteristics
Table 5.1 Absolute Maximum Ratings
Symbol VCC AVCC VI Supply voltage Analog supply voltage Input voltage RESET, CNVSS, BYTE, P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P72-P77, P80P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157(1), VREF, XIN P70, P71 VO Output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140P146, P150-P157(1), XOUT P70, P71 Pd Topr Tstg Power Dissipation Operating ambient temperature Storage temperature Topr=25 C Parameter Condition VCC=AVCC VCC=AVCC Value -0.3 to 6.0 -0.3 to 6.0 -0.3 to VCC+0.3 Unit V V V
-0.3 to 6.0 -0.3 to VCC+0.3 V
-0.3 to 6.0 500 -65 to 150
V mW C
-20 to 85/-40 to 85(2) C
NOTES: 1. P11 to P15 are provided in the 144-pin package. 2. This is an option that is on request basis.
Rev.1.20 Jun. 01, 2004 page 42 of 80
M32C/82 Group
5. Electrical Characteristics
Table 5.2 Recommended Operating Conditions (VCC = 3.0V to 5.5V at Topr = - 20 to 85oC/- 40 to 85oC(3))
Symbol VCC AVCC VSS AVSS VIH Parameter Supply voltage (Through VDC) Supply voltage (Not through VDC) Analog supply voltage Supply voltage Analog supply voltage Input high ("H") P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P72-P77, P80voltage P87(4), P90-P97, P100-P107, P110-P114, P120-P127, P130P137, P140-P146, P150-P157(5), XIN, RESET, CNVSS, BYTE P70, P71 P00-P07, P10-P17 (In single-chip mode) P00-P07, P10-P17 (In memory expansion mode and microprocesor mode) P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80P87(4), P90-P97, P100-P107, P110-P114, P120-P127, P130P137, P140-P146, P150-P157(5), XIN, RESET, CNVSS, BYTE P00-P07, P10-P17 (In single-chip mode) P00-P07, P10-P17 (In memory expansion mode and microprocesor mode) P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110Min 3.0 3.0 Standard Typ 5.0 3.3 VCC 0 0 Max 5.5 3.6 Unit V V V V V V
0.8VCC
VCC
0.8VCC 0.8VCC 0.5VCC 0
6.0 VCC VCC 0.2VCC V V V
VIL
Input low ("L") voltage
0 0
0.2VCC 0.16VCC -10.0
V V mA
IOH(peak)
Peak output high ("H") current(2)
IOH(avg)
IOL(peak)
P114, P120-P127, P130-P137, P140-P146, P150-P157(5) Average output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60high ("H") P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110current(1) P114, P120-P127, P130-P137, P140-P146, P150-P157(5) Peak output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60low ("L") P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110current(2) P114, P120-P127, P130-P137, P140-P146, P150-P157(5) Average output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60low ("L") P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110current(1) P114, P120-P127, P130-P137, P140-P146, P150-P157(5) Main clock Through VDC VCC=4.2 to 5.5V input frequency VCC=3.0 to 5.5V Not through VDC VCC=3.0 to 3.6V
-5.0
mA
10.0
mA
IOL(avg)
5.0
mA
f(XIN)
0 0 0
30 20 20
MHz MHz MHz kHz
f(XCIN) Sub clock oscillation frequency 32.768 50 NOTES: 1. Output current is averaged with 100ms. 2. Total IOL(peak) for P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be less than or equal to 80mA. Total IOH(peak) for P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be less than or equal to -80mA. Total IOL(peak) for P3, P4, P5, P6, P7, P80 to P84, P12 and P13 must be less than or equal to 80mA. Total IOH(peak) for P3, P4, P5, P6, P72 to P77, P80 to P84, P12 and P13 must be less than or equal to -80mA.
3. This is an option that is on request basis. 4. VIH and VIL reference for P87 applies to P87 used as a programmable input ports. It does not apply to P87 used as XCIN. 5. P11 to P15 are provided in the 144-pin package only.
Rev.1.20 Jun. 01, 2004 page 43
of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5 V)
Table 5.3 Electrical Characteristics (VCC=4.2 to 5.5V, VSS=0V at Topr= -20 to 85oC unless otherwise specified)
Symbol VOH Output high ("H") voltage Parameter P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157(1) P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157(1) XOUT XCOUT VOL Output low ("L") voltage Condition VCC=5V IOH=-5mA Min 3.0
VCC = 5V
Unit Max V Typ
Standard
VCC=5V IOH=-200A
4.7
V
VCC=5V IOH=-1mA No load applied
3.0 3.3 2.0
V V V
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- IOL=5mA P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157(1) P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- IOL=200A P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157(1) XOUT XCOUT IOL=1mA No load applied 0.2 0
0.45
V
2.0
V V
VT+-VT-
Hysteresis
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, INT0-INT5, ADTRG, CTS0-CTS4, CLK0-CLK4, TA0OUT-TA4OUT, NMI, KI0-KI3, RxD0-RxD4, SCL0-SCL4, SDA0SDA4 RESET P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- VI=VCC P57, P60-P67, P70-P77, P80-P87, P90-P97, P100P107, P110-P114, P120-P127, P130-P137, P140-
1.0
V
0.2
IIH
Input high ("H") current
1.8 5.0
V A
IIL
P146, P150-P157(1), XIN, RESET, CNVSS, BYTE Input low ("L") current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- VI=0V P57, P60-P67, P70-P77, P80-P87, P90-P97, P100P107, P110-P114, P120-P127, P130-P137, P140P146, P150-P157(1), XIN, RESET, CNVSS, BYTE P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- VI=0V P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157(1) XIN XCIN Through VDC Measurement conditions: f(XIN)=30 MHz, square wave, In single-chip mode, output no division pins are left open and other f(XCIN)=32 kHz, with a wait state, pins are connected to VSS. Topr=25 C Topr=25 C when the clock stops
-5.0
A
RPULLUP
Pull-up resistance
30
50
167
k
RfXIN RfXCIN VRAM ICC
Feedback resistance Feedback resistance RAM standby voltage Power supply current
1.5 10 2.5 28 470 0.4 20 54
M M V mA A A
NOTES: 1. P11 to P15 are provided in the 144-pin package only.
Rev.1.20 Jun. 01, 2004 page 44 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5 V)
VCC = 5V
Table 5.4 A/D Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5V, Vss = AVSS = 0V at Topr = -20 to 85oC unless otherwise specified)
Symbol Resolution Parameter Measurement condition VREF=VCC AN0 to AN7 ANEX0, ANEX1 INL Integral nonlinearity error VREF=VCC=5V External op-amp connection mode DNL RLADDER tCONV tCONV tSAMP VREF VIA Differential nonlinearity error Offset error Gain error Resistor ladder 10-bit conversion time 8-bit conversion time Sample time Reference voltage Analog input voltage VREF=VCC 8 3.3 2.8 0.3 2 0 VCC VREF 7 1 3 3 40 Standard Min Typ Max 10 3 Bits LSB LSB LSB LSB LSB LSB LSB k s s s V V Unit
NOTES: 1. Divide f(XIN), if exceeding 10 MHz, to keep AD frequency less than or equal to 10 MHz.
Table 5.5 D/A Conversion Characteristics (VCC = VREF = 4.2 to 5.5V, VSS = AVSS = 0V at Topr = -20 to 85oC unless otherwise specified)
Symbol tSU RO IVREF Resolution Absolute accuracy Setup time Output resistance Reference power supply input current (Note 1) 4 10 Parameter Measurement condition Standard Min Typ Max 8 1.0 3 20 1.5 Bits % s k mA Unit
NOTES: 1. Mesurement condition is that one of two D/A converters is used and the DAi register (i=0, 1) for the unused D/A converter to "0016". The resistor ladder in the A/D converter is exclued. IVREF flows even if the ADiCON1 register is set to "0" (no VREF connection).
Rev.1.20 Jun. 01, 2004 page 45 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5 V)
VCC = 5V
Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.6 External Clock Input
Symbol tc tw(H) tw(L) tr tf External clock input cycle time External clock input high ("H") pulse width External clock input low ("L") pulse width External clock rising edge time External clock falling edge time Parameter Standard Min 33 13 13 5 5 Max ns ns ns ns ns Unit
Table 5.7 Memory Expansion and Microprocessor Modes
Symbol tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tac3(RD-DB) tac3(AD-DB) tac4(RAS-DB) tac4(CAS-DB) tac4(CAD-DB) tsu(DB-BCLK) tsu(RDY-BCLK) th(RD-DB) th(CAS-DB) th(BCLK-HOLD) td(BCLK-HLDA) Parameter Data input access time (RD standard, with no wait state) Data input access time (AD standard, CS standard, with no wait state) Data input access time (RD standard, with a wait state) Data input access time (AD standard, CS standard, with a wait state) Data input access time (RD standard, when accessing a space with the multiplexed bus) Data input access time (AD standard, CS standard, when accessing a space with the multiplexed bus) Data input access time (RAS standard, when accessing a DRAM space) Data input access time (CAS standard, when accessing a DRAM space) Data input access time (CAD standard, when accessing a DRAM space) Data input setup time RDY input setup time Data input hold time Data input hold time HOLD input hold time HLDA output delay time 26 26 30 0 0 0 0 25 Standard Min Max (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD input setup time
th(BCLK-RDY) RDY input hold time
NOTES: 1. A value can be obtained from the following expressions according to the BCLK frequecncy. Insert a wait state or use lower f(BCLK) as an operation frequency if a calculated value is negative.
tac1(RD - DB) = tac1(AD - DB) =
10 9 f(BCLK) X 2 10 9 f(BCLK)
9
- 35 - 35 - 35 - 35
[ns] [ns] [ns] (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states) [ns] (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states) [ns] (m=3 with 2 wait states and m=5 with 3 wait states) [ns] (n=5 with 2 wait states and n=7 with 3 wait states) [ns] (m=3 with 1 wait state and m=5 with 2 wait states) [ns] (n=1 with 1 wait state and n=3 when 2 wait states) [ns] (l=1 with 1 wait state and l=2 with 2 wait states)
10 X m tac2(RD - DB) = f(BCLK) X 2 tac2(AD - DB) = 10 X n f(BCLK)
9 9
10 X m tac3(RD - DB) = f(BCLK) X 2 - 35 tac3(AD - DB) = tac4(RAS - DB) = tac4(CAS - DB) = tac4(CAD - DB) = 10 9 X n - 35 f(BCLK) X 2 10 9X m f(BCLK) X 2 10 9 X n f(BCLK) X 2 10 9 X l f(BCLK) - 35 - 35 - 35
Rev.1.20 Jun. 01, 2004 page 46 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5 V)
VCC = 5V
Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.8 Timer A Input (Count Source Input in Event Counter Mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Parameter Standard Min 100 40 40 Max ns ns ns Unit
Table 5.9 Timer A Input (Gate Input in Timer Mode)
Standard Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Parameter Min 400 200 200 Max Unit ns ns ns
Table 5.10 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Parameter Min 200 100 100 Max ns ns ns Unit
Table 5.11 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard Symbol tw(TAH) tw(TAL) Parameter Min TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width 100 100 Max ns ns Unit
Table 5.12 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input high ("H") pulse width TAiOUT input low ("L") pulse width TAiOUT input setup time TAiOUT input hold time Parameter Min 2000 1000 1000 400 400 Max ns ns ns ns ns Unit
Rev.1.20 Jun. 01, 2004 page 47 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5 V)
VCC = 5V
Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.13 Timer B Input (Count Source Input in eEvent Counter Mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input high ("H") pulse width (counted on one edge) TBiIN input low ("L") pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high ("H") pulse width (counted on both edges) TBiIN input low ("L") pulse width (counted on both edges) Standard Min 100 40 40 200 80 80 Max Unit ns ns ns ns ns ns
Table 5.14 Timer B Input (Pulse Period Measurement Mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Parameter Standard Min 400 200 200 Max Unit ns ns ns
Table 5.15 Timer B Input (Pulse Width Measurement Mode)
Standard Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Parameter Min 400 200 200 Max ns ns ns Unit
Table 5.16 A/D trigger Input
Symbol tc(AD) tw(ADL) Parameter ADTRG input high ("H") pulse width (trigger available at minimum) ADTRG input low ("L") pulse width Standard Min 1000 125 Max ns ns Unit
Table 5.17 Serial I/O
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-Q) CLKi input cycle time CLKi input high ("H") pulse width CLKi input low ("L") pulse width TxDi output delay time TxDi hold time RxDi input hold time RxDi input hold time
_______
Parameter
Standard Min 200 100 100 80 0 30 90 Max
Unit ns ns ns ns ns ns ns
Table 5.18 External Interrupt INTi Input
Symbol tw(INH) tw(INL) Parameter INTi input high ("H") pulse width INTi input low ("L") pulse width Standard Min 250 250 Max Unit ns ns
Rev.1.20 Jun. 01, 2004 page 48 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5 V)
VCC = 5V
Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.19 Memory Expansion Mode and Microprocessor Mode (with No Wait State)
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) td(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD standard) Chip-select signal output hold time (WR standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal outpu hold time Data output delay time (WR standard) Data outpu hold time (WR standard) Write pulse width -3 (Note 1) (Note 1) (Note 1) -5 18 -2 18 -3 0 (Note 1) 18 -3 0 (Note 1) 18 Measurement condition Standard Min Max 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
See Figure 5.1
NOTES: 1. A value can be obtained from the following expressions according to the BCLK frequency.
td(DB - WR) = th(WR - DB) = th(WR - AD) = th(WR - CS) = tw(WR) =
10 9 f(BCLK)
- 20
[ns] [ns] [ns] [ns] [ns]
10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2
- 10 - 10 - 10 - 15
Rev.1.20 Jun. 01, 2004 page 49 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5 V)
VCC = 5V
Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.20 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory)
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) td(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD standard) Chip-select signal output hold time (WR standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal outpu hold time Data output delay time (WR standard) Data outpu hold time (WR standard) Write pulse width -3 (Note 1) (Note 1) (Note 1) -5 18 -2 18 -3 0 (Note 1) 18 -3 0 (Note 1) 18 Measurement condition Standard Min Max 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
See Figure 5.1
NOTES: 1. A value can be obtained from the following expressions according to the BCLK frequency.
td(DB - WR) = th(WR - DB) = th(WR - AD) = th(WR - CS) =
10 9 X n f(BCLK)
- 20 - 10 - 10 - 10
[ns] (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) [ns] [ns] [ns] [ns] (n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states)
10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 X n f(BCLK) X 2
tw( WR) =
- 15
Rev.1.20 Jun. 01, 2004 page 50 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5 V)
VCC = 5V
Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.21 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory and Selecting a Space with the Multiplexed Bus)
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-AD) td(BCLK-WR) td(BCLK-WR) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) tdz(RD-AD) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD standard) Chip-select signal output hold time (WR standard) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (address standard) ALE signal output hold time (address standard) Address output high-impedance time -2 (Note 1) (Note 1) 8 -3 (Note 1) (Note 1) 18 -3 (Note 1) (Note 1) 18 -5 18 -3 (Note 1) (Note 1) 18 Measurement condition Standard Min Max 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
See Figure 5.1
NOTES: 1. A value can be obtained from the following expressions according to the BCLK frequency.
th(RD - AD) = th(WR - AD) = th(RD - CS) = th(WR - CS) =
10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2
9
- 10 - 10 - 10 - 10
[ns] [ns] [ns] [ns]
td(DB - WR) =
10 X m - 25 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 - 10
[ns] (m=3 with 2 wait states and m=5 with 3 wait states) [ns]
th(WR - DB) =
td(AD - ALE) =
- 20
[ns]
th(ALE - AD) =
- 10
[ns]
Rev.1.20 Jun. 01, 2004 page 51 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5 V)
VCC = 5V
Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.22 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory and Selecting the DRAM Area)
Symbol td(BCLK-AD) th(BCLK-AD) Parameter Row address output delay time Row address output hold time (BCLK standard) -3 18 -3 (Note 1) 18 -3 (Note 1) 18 -3 18 -5 (Note 1) -7 (Note 1) Measurement condition Standard Min Max 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
th(BCLK-CAD) Column address output delay time td(BCLK-CAD) Column address output hold time (BCLK standard) th(RAS-RAD) Row address output hold time after RAS output td(BCLK-RAS) RAS output delay time (BCLK standard) th(BCLK-RAS) RAS output hold time (BCLK standard) tRP RAS high ("H") hold time td(BCLK-CAS) CAS output delay time (BCLK standard) th(BCLK-CAS) CAS output hold time (BCLK standard) td(BCLK-DW) DW output delay time (BCLK standard) th(BCLK-DW) DW output hold time (BCLK standard) tsu(DB-CAS) th(BCLK-DB CAS output setup time after DB output DB signal output hold time (BCLK standard)
See Figure 5.1
tsu(CAS-RAS) CAS output setup time before RAS output (refresh)
NOTES: 1. A value can be obtained from the following expressions according to the BCLK frequency.
th(RAS - RAD) =
10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK)
9
- 13
[ns]
tRP = tsu(DB - CAS) =
X 3 - 20 [ns] [ns]
- 20
tsu(CAS - RAS) =
10 f(BCLK) X 2
- 13
[ns]
Rev.1.20 Jun. 01, 2004 page 52 of 80
M32C/82 Group
5. Electrical Characteristics
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 NOTES: 1. P11 to P15 are provided in the 144-pin package only. Note 1 30pF
Figure 5.1 P0 to P15 Measurement Circuit
Rev.1.20 Jun. 01, 2004 page 53
of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5V)
Vcc=5V
Memory expansion mode and microprocessor mode (with no wait state) Read timing
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max(1) tcyc
th(BCLK-CS)
-3ns.min
CSi
th(RD-CS)
0ns.min
td(BCLK-AD)
ADi BHE
18ns.max(1)
th(BCLK-AD)
-3ns.min
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
tac1(RD-DB)(2) tac1(AD-DB)(2)
DB
Hi-Z
th(BCLK-RD)
-5ns.min
tsu(DB-BCLK)
26ns.min(1)
th(RD-DB)
0ns.min
NOTES: 1. A value is guaranteed with no external factor. Maximum 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. It varies with the operation frequency. tac1(RD-DB)=(tcyc/2-35)ns.max tac1(AD-DB)=(tcyc-35)ns.max
Write timing ( written in 2 cycles with no wait state)
BCLK
18ns.max
td(BCLK-ALE)
ALE
th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
18ns.max
th(BCLK-CS)
-3ns.min
CSi
tcyc
th(WR-CS)(1) th(BCLK-AD)
-3ns.min
td(BCLK-AD)
ADi BHE
18ns.max
td(BCLK-WR)
18ns.max
th(WR-AD)(1) tw(WR)(1) th(BCLK-WR)
-3ns.min
WR,WRL, WRH
td(DB-WR)(1)
DBi NOTES: 1. It varies with the operation frequency. td(DB-WR)=(tcyc-20)ns.min th(WR-DB)=(tcyc/2-10)ns.min th(WR-AD)=(tcyc/2-10)ns.min th(WR-CS)=(tcyc/2-10)ns.min tw(WR)=(tcyc/2-15)ns.min
th(WR-DB)(1)
Measurement conditions * VCC=4.2 to 5.5V * Input high and low voltage: VIH=2.5V, VIL=0.8V * Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 5.2 VCC=5V Timing Diagram (1)
Rev.1.20 Jun. 01, 2004 page 54 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5V)
Vcc=5V
Memory expansion mode and microprocessor mode (with a wait state) Read timing
BCLK
18ns.max
td(BCLK-ALE) th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max(1)
th(BCLK-CS)
-3ns.min
CSi
tcyc
th(RD-CS)
0ns.min
td(BCLK-AD)
ADi BHE
18ns.max(1)
th(BCLK-AD)
-3ns.min
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
tac2(RD-DB)(2) tac2(AD-DB)(2)
DB
Hi-Z
th(BCLK-RD)
-5ns.min
tsu(DB-BCLK)
26ns.min(1)
th(RD-DB)
0ns.min
Notes : 1. A value is guaranteed with no external factor. Maximum 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. It varies with the operation frequency. tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states.) tac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states.)
Write timing (written in 2 cycles with no wait state)
BCLK
18ns.max
td(BCLK-ALE)
ALE
th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
18ns.max
th(BCLK-CS)
-3ns.min
CSi
tcyc
th(WR-CS)(1) th(BCLK-AD)
-3ns.min
td(BCLK-AD)
ADi BHE
18ns.max
td(BCLK-WR)
WR,WRL, WRH
18ns.max
tw(WR)(1)
th(WR-AD)(1) th(BCLK-WR)
-3ns.min
td(DB-WR)(1)
DBi
th(WR-DB)(1)
NOTES: 1. It varies with the operation frequency. td(DB-WR)=(tcyc x n-20)ns.min (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) th(WR-DB)=(tcyc/2-10)ns.min th(WR-AD)=(tcyc/2-10)ns.min th(WR-CS)=(tcyc/2-10)ns.min tw(WR)=(tcyc/2 x n-15)ns.min (n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states)
Measurement conditions * VCC=4.2 to 5.5V * Input high and low voltage: VIH=2.5V, VIL=0 * Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 5.3 VCC=5V Timing Diagram (2)
Rev.1.20 Jun. 01, 2004 page 55 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5V)
Memory expansion mode and microprocessor mode
(with a wait state, when accessing an external memory and using the multiplexed bus)
Vcc=5V
Read timing
BCLK
18ns.max
td(BCLK-ALE)
ALE
th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
18ns.max
tcyc
th(BCLK-CS)
-3ns.min
CSi
th(RD-CS)(1) td(AD-ALE)(1) th(ALE-AD)(1) tdz(RD-AD)
8ns.max
ADi /DBi
Address
Data input
Address
th(RD-DB) tsu(DB-BCLK)
26ns.min 0ns.min
td(BCLK-AD)
ADi BHE
18ns.max
th(BCLK-AD)
-3ns.min
tac3(RD-DB)(1)
tac3(AD-DB)(1)
RD
td(BCLK-RD)
18ns.max
th(BCLK-RD)
-5ns.min
th(RD-AD)(1)
NOTES: 1. It varies with the operation frequency. td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states) tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states)
Write timing (written in 2 cycles with no wait state)
BCLK
18ns.max
td(BCLK-ALE)
ALE
th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
CSi
18ns.max
tcyc
th(BCLK-CS) th(WR-CS)(1)
-3ns.min
td(AD-ALE)(1)
ADi /DBi
th(ALE-AD)(1)
Address Data output Address
td(BCLK-AD)
ADi BHE
18ns.max
td(DB-WR)(1)
th(WR-DB)(1)
th(BCLK-AD)
-3ns.min
td(BCLK-WR)
WR,WRL, WRH
18ns.max
th(BCLK-WR)
-3ns.min
th(WR-AD)(1)
NOTES: 1. It varies with the operation frequency. td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min td(DB-WR)=(tcyc/2 x m-25)ns.min
Measurement conditions * VCC=4.2 to 5.5V * Input high and low voltage: VIH=2.5V, VIL=0.8V * Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 5.4 VCC=5V Timing Diagram (3)
Rev.1.20 Jun. 01, 2004 page 56 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5V)
Memory expansion mode and microprocessor mode
(When accessing the DRAM area)
Vcc=5V
Read timing
BCLK
tcyc
td(BCLK-RAD) th(BCLK-RAD)
18ns.max -3ns.min
td(BCLK-CAD)
18ns.max(1)
th(BCLK-CAD)
-3ns.min
MAi
Row address
Column address
th(RAS-RAD)(2)
RAS
tRP(2) th(BCLK-RAS)
-3ns.min
td(BCLK-RAS)
18ns.max(1)
td(BCLK-CAS)
18ns.max(1)
CASL CASH
th(BCLK-CAS)
-3ns.min
DW
tac4(CAS-DB)(2) tac4(CAD-DB)(2) tac4(RAS-DB)(2)
Hi-Z
DB
tsu(DB-BCLK)
26ns.min(1)
th(CAS-DB)
0ns.min
NOTES: 1. A value is guaranteed with no external factor. Maximum 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). td(BCLK-RAS) + tsu(DB-BCLK) td(BCLK-CAS) + tsu(DB-BCLK) td(BCLK-CAD) + tsu(DB-BCLK) 2. It varies with the operation frequency. tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states) tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states) tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states) th(RAS-RAD)=(tcyc/2-13)ns.min tRP=(tcyc/2 x 3-20)ns.min Measurement conditions * VCC=4.2 to 5.5V * Input high and low voltage: VIH=2.5V, VIL=0.8V * Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 5.5 VCC=5V Timing Diagram (4)
Rev.1.20 Jun. 01, 2004 page 57 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5V)
Memory expansion mode and microprocessor mode
(When accessing the DRAM area)
Vcc=5V
Write timing
BCLK
tcyc
td(BCLK-RAD)
18ns.max
th(BCLK-RAD)
-3ns.min
td(BCLK-CAD)
18ns.max
th(BCLK-CAD)
-3ns.min
MAi
Row address
Column address
th(RAS-RAD)(1)
RAS
tRP(1) th(BCLK-RAS)
-3ns.min
td(BCLK-RAS) td(BCLK-CAS)
18ns.max 18ns.max
CASL CASH
td(BCLK-DW)
18ns.max
th(BCLK-CAS)
-3ns.min
DW
th(BCLK-DW) tsu(DB-CAS)(1)
DB
Hi-Z -5ns.min
th(BCLK-DB)
-7ns.min
NOTES: 1. It varies with the operation frequency. th(RAS-RAD)=(tcyc/2-13)ns.min tRP=(tcyc/2 x 3-20)ns.min tsu(DB-CAS)=(tcyc-20)ns.min Measurement conditions * VCC=4.2 to 5.5V * Input high and low voltage: VIH=2.5V, VIL=0.8V * Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 5.6 VCC=5V Timing Diagram (5)
Rev.1.20 Jun. 01, 2004 page 58 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5V)
Memory expansion mode and microprocessor mode Refresh timing (CAS-before-RAS refresh)
BCLK
Vcc=5V
td(BCLK-RAS)
18ns.max
tcyc
RAS
tsu(CAS-RAS)(1)
CASL CASH
th(BCLK-RAS)
-3ns.min
td(BCLK-CAS)
18ns.max
th(BCLK-CAS)
-3ns.min
DW NOTES : 1. It varies with the operation frequency. tsu(CAS-RAS)=(tcyc/2-13)ns.min
Refresh timing (Self-refresh)
BCLK
td(BCLK-RAS)
18ns.max
tcyc
RAS
th(BCLK-RAS) tsu(CAS-RAS)(1)
CASL CASH
-3ns.min
td(BCLK-CAS)
18ns.max
th(BCLK-CAS)
-3ns.min
DW NOTES: 1. It varies with the operation frequency. tsu(CAS-RAS)=(tcyc/2-13)ns.min Measurement conditions * VCC=4.2 to 5.5V * Input high and low voltage: VIH=2.5V, VIL=0.8V * Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 5.7 VCC=5V Timing Diagram (6)
Rev.1.20 Jun. 01, 2004 page 59 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5V)
tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Counter increment/ decrement input) In event counter mode TAiIN input
(When counting on falling edge is selected)
Vcc=5V
th(TIN-UP)
tsu(UP-TIN)
TAiIN input
(When counting on rising edge is selected)
tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C-Q) RxDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D) th(C-Q)
Figure 5.8 VCC=5V Timing Diagram (7)
Rev.1.20 Jun. 01, 2004 page 60 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 5V)
Vcc=5V
Memory expansion mode and microprocessor mode
(Valid only with a wait state)
BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) (Valid with a wait state or with no wait state) th(BCLK-RDY)
BCLK tsu(HOLD-BCLK) HOLD input th(BCLK-HOLD)
HLDA output P0, P1, P2, P3, P4, P50 to P52
td(BCLK-HLDA)
Hi-Z
td(BCLK-HLDA)
Measurement conditions * VCC=4.2 to 5.5V * Input high and low voltage: VIH=4.0V, VIL=1.0V * Output high and low voltage: VOH=2.5V, VOL=2.5V
Figure 5.9 VCC=5V Timing Diagram (8)
Rev.1.20 Jun. 01, 2004 page 61 of 80
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5. Electrical Characteristics (VCC = 3.3 V)
Table 5.23 Electrical Characteristics (VCC=3.0 to 3.6V, VSS=0V at Topr = -20 to 85oC, unless otherwise specified)
Symbol VOH Output high ("H") voltage Parameter Condition Min 2.7
VCC = 3.3V
Standard Typ Max V Unit
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- IOH=-1mA P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157(1) XOUT IOH=-0.1mA XCOUT No load applied
2.7 3.3 0.5
V V V
VOL
Output low ("L") voltage
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- IOL=1mA P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157(1) XOUT IOL=0.1mA XCOUT No load applied 0.2 0
0.5
V V
VT+-VT-
Hysteresis
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, INT0-INT5, ADTRG, CTS0-CTS4, CLK0-CLK4, TA0OUT-TA4OUT, NMI, KI0-KI3, RxD0-RxD4, SCL0-SCL4, SDA0SDA4 RESET P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- VI=VCC P57, P60-P67, P70-P77, P80-P87, P90-P97, P100P107, P110-P114, P120-P127, P130-P137, P140-
1.0
V
0.2
IIH
Input high ("H") current
1.8 4.0
V A
IIL
P146, P150-P157(1), XIN, RESET, CNVSS, BYTE Input low ("L") current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- VI=0V P57, P60-P67, P70-P77, P80-P87, P90-P97, P100P107, P110-P114, P120-P127, P130-P137, P140P146, P150-P157(1), XIN, RESET, CNVSS, BYTE P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- VI=0V P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157(1) XIN XCIN Through VDC Not through VDC Measurement condition: In single-chip mode, output pins are left open and other pins are connected to VSS.
-4.0
A
RPULLUP
Pull-up resistance
66
120
500
k
RfXIN RfXCIN VRAM ICC
Feedback resistance Feedback resistance RAM standby voltage Power supply current
3.0 20.0 2.5 2.0 f(XIN)=20 MHz, square wave, no division f(XCIN)=32 kHz, with a wait state, not through VDC, Topr=25 C f(XCIN)=32 kHz, with a wait state, through VDC, Topr=25 C Topr=25 C when the clock stops 17 5.0 340 0.4 20 38
M M V mA A A A
NOTES: 1. P11 to P15 are provided in the 144-pin package only.
Rev.1.20 Jun. 01, 2004 page 62 of 80
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5. Electrical Characteristics (VCC = 3.3 V)
VCC = 3.3V
Table 5.24 A/D Conversion Characteristics (VCC = AVCC = VREF = 3.0 to 3.6V, VSS = AVSS = 0V at Topr = -20 to 85oC unless otherwise specified)
Symbol INL DNL RLADDER tCONV VREF VIA Resolution Integral nonlinearity error Differential nonlinearity error Offset error Gain error Resistor ladder 8-bit conversion time Reference voltage Analog input voltage Parameter Measurement condition VREF=VCC No S&H function (8-bit) VCC=VREF=3.3V No S&H function (8-bit) No S&H function (8-bit) No S&H function (8-bit) VREF=VCC 8 4.9 3.0 0 VCC VREF Standard Min Typ Max 10 2 1 2 2 40 Bits LSB LSB LSB LSB k s V V Unit
S&H: Sample and hold NOTES: 1. Divide f(XIN), if exceeding 10 MHz, to keep AD frequency less than or equal to 10 MHz.
Table 5.25 D/A Conversion Characteristics (VCC = VREF = 3.0 to 3.6V, VSS = AVSS = 0V at Topr = -20 to 85oC unless otherwise specified)
Symbol tSU RO IVREF Resolution Absolute accuracy Setup time Output resistance Reference power supply input current (Note 1) 4 10 Parameter Measurement condition Standard Min Typ Max 8 1.0 3 20 1. 0 Bits % s k mA Unit
NOTES: 1. Mesurement condition is that one of two D/A converters is used and the DAi register (i=0, 1) for the unused D/A converter to "0016". The resistor ladder in the A/D converter is exclued. IVREF flows even if the ADiCON1 register is set to "0" (no VREF connection).
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5. Electrical Characteristics (VCC = 3.3 V)
Timing Requirements (VCC = 3.0 to 3.6V, VSS = 0V at Topr = -20 to Table 5.26 External Clock Input
Symbol tc tw(H) tw(L) tr tf External clock input cycle time External clock input high ("H") pulse width External clock input low ("L") pulse width External clock rising-edge time External clock falling-edge time Parameter
85oC
VCC = 3.3V
unless otherwise specified)
Standard Min 50 22 22 5 5 Max
Unit ns ns ns ns ns
Table 5.27 Memory Expansion Mode and Microprocessor Mode
Symbol tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tac3(RD-DB) tac3(AD-DB) tac4(RAS-DB) tac4(CAS-DB) tac4(CAD-DB) tsu(DB-BCLK) tsu(RDY-BCLK) th(RD-DB) th(CAS-DB) th(BCLK-HOLD) td(BCLK-HLDA) Parameter Data input access time (RD standard, with no wait state) Data input access time (AD standard, CS standard, with no wait state) Data input access time (RD standard, with a wait state) Data input access time (AD standard, CS standard, with a wait state) Data input access time (RD standard, when accessing a space with the multiplexed bus) Data input access time (AD standard, CS standard, when accessing a space with the multiplexed bus) Data input access time (RAS standard, when accessing a DRAM space) Data input access time (CAS standard, when accessing a DRAM space) Data input access time (CAD standard, when accessing a DRAM space) Data input setup time RDY input setup time Data input hold time Data input hold time HOLD input hold time HLDA output delay time 30 40 60 0 0 0 0 25 Standard Min Max (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD input setup time
th(BCLK-RDY) RDY input hold time
NOTES: 1. A value can be obtained from the following expressions according to the BCLK frequecncy. Insert a wait state or use lower f(BCLK) as an operation frequency if a calculated value is negative.
tac1(RD - DB) = tac1(AD - DB) =
10 9 f(BCLK) X 2 10 9 f(BCLK)
9
- 35 - 35 - 35 - 35
[ns] [ns] [ns] (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states) [ns] (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states) [ns] (m=3 with 2 wait states and m=5 with 3 wait states) [ns] (n=5 with 2 wait states and n=7 with 3 wait states) [ns] (m=3 with 1 wait state and m=5 with 2 wait states) [ns] (n=1 with 1 wait state and n=3 when 2 wait states) [ns] (l=1 with 1 wait state and l=2 with 2 wait states)
10 X m tac2(RD - DB) = f(BCLK) X 2 tac2(AD - DB) = 10 X n f(BCLK)
9 9
10 X m tac3(RD - DB) = f(BCLK) X 2 - 35 tac3(AD - DB) = tac4(RAS - DB) = tac4(CAS - DB) = tac4(CAD - DB) = 10 9 X n - 35 f(BCLK) X 2 10 9X m f(BCLK) X 2 10 9 X n f(BCLK) X 2 10 9 X l f(BCLK) - 35 - 35 - 35
Rev.1.20 Jun. 01, 2004 page 64 of 80
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5. Electrical Characteristics (VCC = 3.3 V)
VCC = 3.3V
Timing Requirements (VCC = 3.0 to 3.6V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.28 Timer A Input (Count Source Input in Event Counter Mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Parameter Standard Min 100 40 40 Max ns ns ns Unit
Table 5.29 Timer A Input (Gate Input in Timer Mode)
Standard Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Parameter Min 400 200 200 Max Unit ns ns ns
Table 5.30 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Parameter Min 200 100 100 Max ns ns ns Unit
Table 5.31 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard Symbol tw(TAH) tw(TAL) Parameter Min TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width 100 100 Max ns ns Unit
Table 5.32 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input high ("H") pulse width TAiOUT input low ("L") pulse width TAiOUT input setup time TAiOUT input hold time Parameter Min 2000 1000 1000 400 400 Max ns ns ns ns ns Unit
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M32C/82 Group
5. Electrical Characteristics (VCC = 3.3 V)
VCC = 3.3V
Timing Requirements (VCC = 3.0 to 3.6V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.33 Timer B input (Count Source Input in Event Counter Mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input high ("H") pulse width (counted on one edge) TBiIN input low ("L") pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high ("H") pulse width (counted on both edges) TBiIN input low ("L") pulse width (counted on both edges) Standard Min 100 40 40 200 80 80 Max Unit ns ns ns ns ns ns
Table 5.34 Timer B input (Pulse Period Measurement Mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Parameter Standard Min 400 200 200 Max Unit ns ns ns
Table 5.35 Timer B input (Pulse Width Measurement Mode)
Standard Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Parameter Min 400 200 200 Max ns ns ns Unit
Table 5.36 A/D Trigger Input
Symbol tc(AD) tw(ADL) Parameter ADTRG input high ("H") pulse width (trigger available at minimum) ADTRG input low ("L") pulse width Standard Min 1000 125 Max ns ns Unit
Table 5.37 Serial I/O
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-Q) CLKi input cycle time CLKi input high ("H") pulse width CLKi input low ("L") pulse width TxDi output delay time TxDi hold time RxDi input hold time RxDi input hold time
_______
Parameter
Standard Min 200 100 100 80 0 30 90 Max
Unit ns ns ns ns ns ns ns
Table 5.38 External Interrupt INTi input
Symbol tw(INH) tw(INL) Parameter INTi input high ("H") pulse width INTi input low ("L") pulse width Standard Min 250 250 Max Unit ns ns
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5. Electrical Characteristics (VCC = 3.3 V)
VCC = 3.3V
Switching Characteristics (VCC = 3.0 to 3.6V, VSS = 0V at Topr = -20 to 85oC, unless otherwise specified) Table 5.39 Memory Expansion Mode and Microprocessor Mode (with No Wait State)
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) td(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD standard) Chip-select signal output hold time (WR standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal outpu hold time Data output delay time (WR standard) Data outpu hold time (WR standard) Write pulse width 0 (Note 1) (Note 1) (Note 1) -3 18 -2 18 0 0 (Note 1) 18 0 0 (Note 1) 18 Measurement condition Standard Min Max 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
See Figure 5.1
NOTES: 1. A value can be obtained from the following expressions according to the BCLK frequency.
td(DB - WR) = th(WR - DB) = th(WR - AD) = th(WR - CS) =
10 9 f(BCLK)
- 20
[ns] [ns] [ns] [ns]
10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2
- 10 - 10 - 10
tw(WR) =
- 15
[ns]
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M32C/82 Group
5. Electrical Characteristics (VCC = 3.3 V)
VCC = 3.3V
Switching Characteristics (VCC = 3.0 to 3.6V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.40 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory)
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) td(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD standard) Chip-select signal output hold time (WR standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal outpu hold time Data output delay time (WR standard) Data outpu hold time (WR standard) Write pulse width 0 (Note 1) (Note 1) (Note 1) -3 18 0 0 (Note 1) 18 -2 18 0 0 (Note 1) 18 Measurement condition Standard Min Max 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
See Figure 5.1
NOTES: 1. A value can be obtained from the following expressions according to the BCLK frequency.
td(DB - WR) = th(WR - DB) = th(WR - AD) = th(WR - CS) =
10 9 X n f(BCLK)
- 20 - 10 - 10 - 10
10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 X n f(BCLK) X 2
[ns] (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) [ns] [ns] [ns]
tw( WR) =
- 15 [ns] (n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states)
Rev.1.20 Jun. 01, 2004 page 68 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 3.3 V)
VCC = 3.3V
Switching Characteristics (VCC = 3.0 to 3.6V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.41 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory and Selecting a Space with the Multiplexed Bus)
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-AD) td(BCLK-WR) td(BCLK-WR) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) tdz(RD-AD) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD standard) Chip-select signal output hold time (WR standard) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (address standard) ALE signal output hold time (address standard) Address output high-impedance time -2 (Note 1) (Note 1) 8 0 (Note 1) (Note 1) 18 0 (Note 1) (Note 1) 18 -3 18 0 (Note 1) (Note 1) 18 Measurement condition Standard Min Max 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
See Figure 5.1
NOTES: 1. A value can be obtained from the following expressions according to the BCLK frequency.
th(RD - AD) = th(WR - AD) = th(RD - CS) = th(WR - CS) =
10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2
9
- 10 - 10 -10 - 10
[ns] [ns] [ns] [ns]
td(DB - WR) =
10 X m - 25 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 10 9 f(BCLK) X 2 - 10
[ns] (m=3 with 2 wait states and m=5 with 3 wait states)
th(WR - DB) =
[ns]
td(AD - ALE) =
- 20
[ns]
th(ALE - AD) =
- 10
[ns]
Rev.1.20 Jun. 01, 2004 page 69 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 3.3 V)
VCC = 3.3V
Switching Characteristics (VCC = 3.0 to 3.6V, VSS = 0V at Topr = -20 to 85oC unless otherwise specified) Table 5.42 Memory Expansion Mode and Microprocessor Mode (With a Wait State, Accessing an External Memory and Selecting the DRAM Area)
Symbol td(BCLK-AD) th(BCLK-AD) th(BCLK-CAD) td(BCLK-CAD) th(RAS-RAD) td(BCLK-RAS) th(BCLK-RAS) tRP td(BCLK-CAS) th(BCLK-CAS) td(BCLK-DW) th(BCLK-DW) tsu(DB-CAS) th(BCLK-DB tsu(CAS-RAS) Parameter Row address output delay time Row address output hold time (BCLK standard) Column address output delay time Column address output hold time (BCLK standard) Row address output hold time after RAS output RAS output delay time (BCLK standard) RAS output hold time (BCLK standard) RAS high ("H") hold time CAS output delay time (BCLK standard) CAS output hold time (BCLK standard) DW output delay time (BCLK standard) DW output hold time (BCLK standard) CAS output setup time after DB output DB signal output hold time (BCLK standard) CAS output setup time before RAS output (refresh) -3 (Note 1) -7 (Note 1) 0 18 0 (Note 1) 18 0 (Note 1) 18 0 18 Measurement condition Standard Min Max 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
See Figure 5.1
NOTES: 1. A value can be obtained from the following expressions according to the BCLK frequency.
th(RAS - RAD) =
10 9 f(BCLK) X 2 10 9 X 3 f(BCLK) X 2 10 9 f(BCLK)
9
- 13
[ns]
tRP = tsu(DB - CAS) =
- 20 [ns] [ns]
- 20
tsu(CAS - RAS) =
10 f(BCLK) X 2
- 13
[ns]
Rev.1.20 Jun. 01, 2004 page 70 of 80
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5. Electrical Characteristics (VCC = 3.3V)
Vcc=3.3V
Memory expansion mode and microprocessor mode (with no wait state) Read timing
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max(1)
th(BCLK-CS)
0ns.min
CSi
tcyc
th(RD-CS)
0ns.min
td(BCLK-AD)
ADi BHE
18ns.max(1)
th(BCLK-AD)
0ns.min
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
tac2(RD-DB)(2) tac2(AD-DB)(2)
DB
Hi-Z
th(BCLK-RD)
-3ns.min
tsu(DB-BCLK)
30ns.min(1)
th(RD-DB)
0ns.min
NOTES: 1. A value is guarantee with no external factor. Maximum 35ns is garanteed for td(BCLK-AD)+tsu(DB-BCLK). 2. It varies with the operation frequency. tac2(RD-DB)=(tcyc/2-35)ns.max tac2(AD-DB)=(tcyc-35)ns.max
Write timing
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max
th(BCLK-CS)
0ns.min
CSi
tcyc
th(WR-CS)(1) th(BCLK-AD)
0ns.min
td(BCLK-AD)
ADi BHE
18ns.max
td(BCLK-WR)
18ns.max
tw(WR)(1)
th(WR-AD)(1) th(BCLK-WR)
0ns.min
WR,WRL, WRH
td(DB-WR)(1)
DBi NOTES: 1. It varies with the operation frequency. td(DB-WR)=(tcyc-20)ns.min th(WR-DB)=(tcyc/2-10)ns.min th(WR-AD)=(tcyc/2-10)ns.min th(WR-CS)=(tcyc/2-10)ns.min tw(WR)=(tcyc/2-15)ns.min
th(WR-DB)(1)
Measurement conditions * VCC=3.0 to 3.6V * Input high and low voltage: VIH=1.5V, VIL=0.5V * Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 5.10 VCC=3.3V Timing Diagram (1)
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M32C/82 Group
5. Electrical Characteristics (VCC = 3.3V)
Vcc=3.3V
Memory expansion mode and microprocessor mode (with a wait state) Read timing
BCLK
18ns.max
td(BCLK-ALE) th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max(1)
th(BCLK-CS)
0ns.min
CSi
tcyc
th(RD-CS)
0ns.min
td(BCLK-AD)
ADi BHE
18ns.max(1)
th(BCLK-AD)
0ns.min
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
tac2(RD-DB)(2) tac2(AD-DB)(2)
DB
Hi-Z
th(BCLK-RD)
-3ns.min
tsu(DB-BCLK)
30ns.min(1)
th(RD-DB)
0ns.min
NOTES: 1. A value is guarantee with no external factor. Maximum 35ns is garanteed for td(BCLK-AD)+tsu(DB-BCLK). 2. It varies with the operation frequency. tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states) tac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states)
Write timing
BCLK
18ns.max
td(BCLK-ALE)
ALE
th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
18ns.max
th(BCLK-CS)
0ns.min
CSi
tcyc
th(WR-CS)(1) th(BCLK-AD)
0ns.min
td(BCLK-AD)
18ns.max
ADi BHE
td(BCLK-WR) tw(WR)(1)
WR,WRL, WRH
18ns.max
th(WR-AD)(1) th(BCLK-WR)
0ns.min
td(DB-WR)
DBi
(1)
th(WR-DB)(1)
NOTES: 1. It varies with the operation frequency. td(DB-WR)=(tcyc x n-20)ns.min (n=1 when 1 wait, n=2 with 2 wait states and n=3 with 3 wait states) th(WR-DB)=(tcyc/2-10)ns.min th(WR-AD)=(tcyc/2-10)ns.min th(WR-CS)=(tcyc/2-10)ns.min tw(WR)=(tcyc/2 x n-15)ns.min (n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states)
Measurement conditions * VCC=3.0 to 3.6V * Input high and low voltage: VIH=1.5V, VIL=0.5V * Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 5.11 VCC=3.3V Timing Diagram (2)
Rev.1.20 Jun. 01, 2004 page 72 of 80
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5. Electrical Characteristics (VCC = 3.3V)
Memory expansion mode and microprocessor mode
(with a wait state, when accessing an external memory and using the multiplexed bus)
Vcc=3.3V
Read timing
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min tcyc
ALE
td(BCLK-CS)
18ns.max
th(BCLK-CS)
0ns.min
CSi
th(RD-CS)(1) td(AD-ALE)(1) th(ALE-AD)(1) tdz(RD-AD)
8ns.max
ADi /DBi
Address
Data input
Address
th(RD-DB) tsu(DB-BCLK)
30ns.min 0ns.min
td(BCLK-AD)
ADi BHE
18ns.max
th(BCLK-AD)
0ns.min
tac3(RD-DB)(1)
tac3(AD-DB)(1)
RD
td(BCLK-RD)
18ns.max
th(BCLK-RD)
-3ns.min
th(RD-AD)(1)
NOTES: 1. It varies with the operation frequency. td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states) tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states)
Write Timing
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
CSi
18ns.max
tcyc
th(BCLK-CS) th(WR-CS)(1)
0ns.min
td(AD-ALE)(1) th(ALE-AD)(1)
ADi /DBi Address Data output Address
td(BCLK-AD)
ADi BHE
18ns.max
td(DB-WR)(1)
th(WR-DB)(1)
th(BCLK-AD)
0ns.min
td(BCLK-WR)
WR,WRL, WRH
18ns.max
th(BCLK-WR)
0ns.min
th(WR-AD)()
NOTES: 1. It varies with the operation frequency. td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min td(DB-WR)=(tcyc/2 x m-25)ns.min (m=3 with 2 wait states and m=5 with 3 wait states)
Measurement conditions * VCC=3.0 to 3.6V * Input high and low voltage: VIH=1.5V, VIL=0.5V * Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 5.12 VCC=3.3V Timing Diagram (3)
Rev.1.20 Jun. 01, 2004 page 73 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 3.3V)
Memory expansion mode and microprocessor mode
(With 2 wait states, when accessing the DRAM area)
Vcc=3.3V
Read timing
BCLK
tcyc
td(BCLK-RAD)
18ns.max
th(BCLK-RAD)
(1)
td(BCLK-CAD)
18ns.max(1)
th(BCLK-CAD)
0ns.min
0ns.min
MAi
Row address
Column address
th(RAS-RAD)
RAS
(1)
tRP(2) th(BCLK-RAS)
0ns.min
td(BCLK-RAS)
18ns.max(1)
td(BCLK-CAS)
18ns.max(1)
CASL CASH
th(BCLK-CAS)
0ns.min
DW
tac4(CAS-DB)(2) tac4(CAD-DB)(2) tac4(RAS-DB)(2)
Hi-Z
DB
tsu(DB-BCLK)
30ns.min(1)
th(CAS-DB)
0ns.min
NOTES: 1. A value is guaranteed with no external factor. Maximum 35ns is garanteed for the followings: td(BCLK-RAS) + tsu(DB-BCLK) td(BCLK-CAS) + tsu(DB-BCLK) td(BCLK-CAD) + tsu(DB-BCLK) 2. It varies with the operation frequency. tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states) tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states) tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states) th(RAS-RAD)=(tcyc/2-13)ns.min tRP=(tcyc/2 x 3-20)ns.min Measurement conditions * VCC=3.0 to 3.6V * Input high and low voltage: VIH=1.5V, VIL=0.5V * Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 5.13 VCC=3.3V Timing Diagram (4)
Rev.1.20 Jun. 01, 2004 page 74 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 3.3V)
Memory expansion mode and microprocessor mode
(With 2 wait states, when accessing the DRAM area)
Vcc=3.3V
Write timing
BCLK
tcyc
td(BCLK-RAD)
18ns.max
th(BCLK-RAD)
0ns.min
td(BCLK-CAD)
18ns.max
th(BCLK-CAD)
0ns.min
MAi
Row address
Column address
th(RAS-RAD)(1)
RAS
tRP(1)
td(BCLK-RAS) td(BCLK-CAS)
18ns.max 18ns.max
th(BCLK-RAS)
0ns.min
CASL CASH
td(BCLK-DW)
18ns.max
th(BCLK-CAS)
0ns.min
DW
th(BCLK-DW) tsu(DB-CAS)(1)
DB
Hi-Z -3ns.min
th(BCLK-DB)
-7ns.min
NOTES: 1. It varies with the operation frequency. th(RAS-RAD)=(tcyc/2-13)ns.min tRP=(tcyc/2 x 3-20)ns.min tsu(DB-CAS)=(tcyc-20)ns.min
Measurement conditions * VCC=3.0 to 3.6V * Input high and low voltage: VIH=1.5V, VIL=0.5V * Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 5.14 VCC=3.3V Timing Diagram (5)
Rev.1.20 Jun. 01, 2004 page 75 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 3.3V)
Memory expansion mode and microprocessor mode Vcc=3.3V Refresh timing (CAS-before-RAS refresh)
BCLK
td(BCLK-RAS)
18ns.max
tcyc
RAS
tsu(CAS-RAS)(1)
CASL CASH
th(BCLK-RAS)
0ns.min
td(BCLK-CAS)
18ns.max
th(BCLK-CAS)
0ns.min
DW NOTES: 1. It varies with the operation frequency. tsu(CAS-RAS)=(tcyc/2-13)ns.min
Refresh timing (Self-refresh)
BCLK
td(BCLK-RAS)
18ns.max
tcyc
RAS
tsu(CAS-RAS)(1)
CASL CASH
th(BCLK-RAS)
0ns.min
td(BCLK-CAS)
18ns.max
th(BCLK-CAS)
0ns.min
DW NOTES: 1. It varies with the operation frequency. tsu(CAS-RAS)=(tcyc/2-13)ns.min Measurement conditions * VCC=3.0 to 3.6V * Input high and low voltage: VIH=1.5V, VIL=0.5V * Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 5.15 VCC=3.3V Timing Diagram (6)
Rev.1.20 Jun. 01, 2004 page 76 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 3.3V)
tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Counter increment/ decrement input) In event counter mode TAiIN input
(When counting on falling edge is selected)
Vcc=3.3V
th(TIN-UP)
tsu(UP-TIN)
TAiIN input
(When counting on rising edge is selected)
tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C-Q) RxDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D) th(C-Q)
Figure 5.16 VCC=3.3V Timing Diagram (7)
Rev.1.20 Jun. 01, 2004 page 77 of 80
M32C/82 Group
5. Electrical Characteristics (VCC = 3.3V)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode
(Valid only with a wait state)
BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) (Valid with a wait state and no wait state) th(BCLK-RDY)
BCLK tsu(HOLD-BCLK) HOLD input th(BCLK-HOLD)
HLDA output P0, P1, P2, P3, P4, P50 to P52 td(BCLK-HLDA) td(BCLK-HLDA)
Hi-Z
Measurement conditions * VCC=3.0 to 3.6V * Input high or low voltage: VIH=2.4V, VIL=0.6V * Output high or low voltage: VOH=1.5V, VOL=1.5V
Figure 5.17 VCC=3.3V Timing Diagram (8)
Rev.1.20 Jun. 01, 2004 page 78 of 80
M32C/82 Group
Package Dimensions
Package Dimensions
144P6Q-A
Recommended
JEDEC Code - HD Weight(g) 1.23 Lead Material Cu Alloy
Plastic 144pin 2020mm body LQFP
MD
e
EIAJ Package Code LQFP144-P-2020-0.50
144
109
1
108
b2
D
l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
36
73
37
72
A F
L1
e
x y b2 I2 MD ME
y
b
x
M
L Detail F
Lp
Dimension in Millimeters Min Nom Max 1.7 - - 0.125 0.2 0.05 1.4 - - 0.17 0.22 0.27 0.105 0.125 0.175 19.9 20.0 20.1 19.9 20.0 20.1 0.5 - - 21.8 22.0 22.2 21.8 22.0 22.2 0.35 0.5 0.65 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 0.1 - - 0 8 - 0.225 - - 0.95 - - 20.4 - - - - 20.4
HE
E
A2
A1
100P6S-A
Recommended
JEDEC Code - HD D Weight(g) 1.58 Lead Material Alloy 42
c
A3
Plastic 100pin 1420mm body QFP
MD
EIAJ Package Code QFP100-P-1420-0.65
e
1
80
b2
100
81
I2 Recommended Mount Pad Symbol Dimension in Millimeters Min Nom Max - - 3.05 0.1 0.2 0 - - 2.8 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.65 - - 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 - - - - 0.13 - - 0.1 - 0 10 - - 0.35 1.3 - - - - 14.6 - - 20.6
HE
E
30
51
31
50
A
L1
A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME
A2
F
b
A1
e y
x
M
Detail F
Rev.1.20 Jun. 01, 2004 page 79 of 80
c
L
ME
ME
M32C/82 Group
Package Dimensions
100P6Q-A
Recommended
JEDEC Code - Weight(g) 0.63 Lead Material Cu Alloy
Plastic 100pin 1414mm body LQFP
MD
e
EIAJ Package Code LQFP100-P-1414-0.50
D
100 76
1
75
b2
HD
l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
A3
25
51
26
50
A e F
A2
L1
x y b2 I2 MD ME
M
Detail F
Lp
Rev.1.20 Jun. 01, 2004 page 80 of 80
c
b
x
y
L
Dimension in Millimeters Min Nom Max 1.7 - - 0.1 0.2 0 1.4 - - 0.13 0.18 0.28 0.105 0.125 0.175 13.9 14.0 14.1 13.9 14.0 14.1 0.5 - - 15.8 16.0 16.2 15.8 16.0 16.2 0.3 0.5 0.7 1.0 - - 0.6 0.75 0.45 0.25 - - - - 0.08 0.1 - - 0 10 - 0.225 - - 0.9 - - 14.4 - - - - 14.4
HE
E
A1
ME
REVISION HISTORY
Rev.
1.00 1.10
M32C/82 Group Short Sheet/Data Sheet
Description Summary
Date Page
15/07/2003 30/09/2003
New Document Overview 2 - "1.2 Difference between the M32C/82 Group and the M32C/83 Group" has been added. 3 to 4 - "DRAMC" and "Oscillator stop detect function" have been added to Tables 1.1 and 1.2 11,15 - VREF pin has been changed from analog input pin to control pin. 17,18 - SDA0 to SDA4 pins have been changed from output pins to I/O pins. 18 - Description of intelligent I/O has been modified. 20 - BEIN and BEOUT pins have been modified to IEIN and IEOUT pins in port P13. SFR 28 - Value after RLVL register reset has been modified. Electrical Characteristics 42 - Maximum value of sub clock oscillation frequency has been added in Table 5.2. 1.20 Jun. 01, 2004 All pages Words standardized: On-chip oscillator, A/D converter and D/A converter
-
A-1
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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